From patchwork Mon Feb 12 06:01:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vijay Viswanath X-Patchwork-Id: 10211845 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CB609602CB for ; Mon, 12 Feb 2018 06:02:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B949328917 for ; Mon, 12 Feb 2018 06:02:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AE15928B4A; Mon, 12 Feb 2018 06:02:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1E80C28917 for ; Mon, 12 Feb 2018 06:02:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932882AbeBLGBp (ORCPT ); Mon, 12 Feb 2018 01:01:45 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:35934 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932880AbeBLGBm (ORCPT ); Mon, 12 Feb 2018 01:01:42 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id B855860F8D; Mon, 12 Feb 2018 06:01:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1518415301; bh=Wuk+EAefzrRuoKDL/BIPBhJEIiRsM0GbAQu8Scfih2I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=J/2K7CaxCl0E3HvOCPcTrnqk6+8kO2R0wuHIRhBlQoHynw0AtZrV5FLTGL32gtr4q Vuq7u3IlH6nH82XcVoRS3o1YpIbAYl7M2sVw2LSOZAmBZBuBDHTJwKjICLctVxHHv+ /XPXpdMQtVxuYe0Jh5/fBRTMbXucYLMfJTZHHi1c= Received: from hydcbspbld03.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: vviswana@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 0029960F71; Mon, 12 Feb 2018 06:01:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1518415300; bh=Wuk+EAefzrRuoKDL/BIPBhJEIiRsM0GbAQu8Scfih2I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=byNal5xv38E+0C6AtBYm+vmYS1PbnGawdKJ9Fr1BHmh2NzpeTwU3wqzZpUmnYVUmU 4DYBPWeFJJkqRMF2uT3SNXWAsk1h/EKT9jhQqNFcVX7JkvD/fy+fPP9o/QZqfbomVv VHeIbLet8PtbEClwUkmIgmVUsWYNUXk76MkiADlg= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 0029960F71 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vviswana@codeaurora.org From: Vijay Viswanath To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, shawn.lin@rock-chips.com, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org, asutoshd@codeaurora.org, stummala@codeaurora.org, venkatg@codeaurora.org, pramod.gurav@linaro.org, jeremymc@redhat.com, vviswana@codeaurora.org, Krishna Konda Subject: [PATCH V2 2/2] mmc: sdhci-msm: support voltage pad switching Date: Mon, 12 Feb 2018 11:31:18 +0530 Message-Id: <1518415278-59062-3-git-send-email-vviswana@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518415278-59062-1-git-send-email-vviswana@codeaurora.org> References: <1518415278-59062-1-git-send-email-vviswana@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Krishna Konda The PADs for SD card are dual-voltage that support 3v/1.8v. Those PADs have a control signal (io_pad_pwr_switch/mode18 ) that indicates whether the PAD works in 3v or 1.8v. SDHC core on msm platforms should have IO_PAD_PWR_SWITCH bit set/unset based on actual voltage used for IO lines. So when power irq is triggered for io high or io low, the driver should check the voltages supported and set the pad accordingly. Signed-off-by: Krishna Konda Signed-off-by: Venkat Gopalakrishnan Signed-off-by: Vijay Viswanath --- drivers/mmc/host/sdhci-msm.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 5c23e92..96c81df 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -78,6 +78,8 @@ #define CORE_HC_MCLK_SEL_DFLT (2 << 8) #define CORE_HC_MCLK_SEL_HS400 (3 << 8) #define CORE_HC_MCLK_SEL_MASK (3 << 8) +#define CORE_IO_PAD_PWR_SWITCH_EN (1 << 15) +#define CORE_IO_PAD_PWR_SWITCH (1 << 16) #define CORE_HC_SELECT_IN_EN BIT(18) #define CORE_HC_SELECT_IN_HS400 (6 << 19) #define CORE_HC_SELECT_IN_MASK (7 << 19) @@ -1109,6 +1111,7 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq) u32 irq_status, irq_ack = 0; int retry = 10; int pwr_state = 0, io_level = 0; + u32 config = 0; irq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS); @@ -1166,6 +1169,30 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq) */ writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL); + /* Ensure order between core_mem and hc_mem */ + mb(); + /* + * We should unset IO PAD PWR switch only if the register write can + * set IO lines high and the regulator also switches to 3 V. + * Else, we should keep the IO PAD PWR switch set. + * This is applicable to certain targets where eMMC vccq supply is only + * 1.8V. In such targets, even during REQ_IO_HIGH, the IO PAD PWR + * switch must be kept set to reflect actual regulator voltage. This + * way, during initialization of controllers with only 1.8V, we will + * set the IO PAD bit without waiting for a REQ_IO_LOW. + */ + config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC); + + if ((io_level & REQ_IO_HIGH) && (msm_host->caps_0 & CORE_3_0V_SUPPORT)) + config &= ~CORE_IO_PAD_PWR_SWITCH; + else if ((io_level & REQ_IO_LOW) || + (msm_host->caps_0 & CORE_1_8V_SUPPORT)) + config |= CORE_IO_PAD_PWR_SWITCH; + + writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC); + /* Ensure IO pad update before any further register read/writes */ + mb(); + if (pwr_state) msm_host->curr_pwr_state = pwr_state; if (io_level) @@ -1518,6 +1545,13 @@ static int sdhci_msm_probe(struct platform_device *pdev) } /* + * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH bit can + * be used as required later on. + */ + config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC); + config |= CORE_IO_PAD_PWR_SWITCH_EN; + writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC); + /* * Power on reset state may trigger power irq if previous status of * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq * interrupt in GIC, any pending power irq interrupt should be