From patchwork Wed Feb 14 13:59:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilia Lin X-Patchwork-Id: 10218971 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 630A26055C for ; Wed, 14 Feb 2018 14:00:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5381528FD7 for ; Wed, 14 Feb 2018 14:00:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5196F28FE7; Wed, 14 Feb 2018 14:00:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 76B8128FE2 for ; Wed, 14 Feb 2018 14:00:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030576AbeBNOAm (ORCPT ); Wed, 14 Feb 2018 09:00:42 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:43616 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030632AbeBNOAc (ORCPT ); Wed, 14 Feb 2018 09:00:32 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 91DBD60FEB; Wed, 14 Feb 2018 14:00:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1518616827; bh=0zL8ShgCa8ox73QztcksRqRCbLfIm6bNCMDqEVkMhNs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=K26YjW7yGXhpyqYp1lY561VkOIvIQIL2chUK1ptaxQ7sQ4PvboFuH4c4GJLwVgkfi ldQDNAJw/CBt8Y4nqO7mNKjDC25UEkqvIBuh6nX6IYNYafJyQBAV5HtTn9ZJnFjcsN ByFOszgWACmg5tmqauLKISCMnzEIOnJLbhpH02R0= Received: from lx-ilial.mea.qualcomm.com (unknown [185.23.60.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilialin@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 77FEA60F6D; Wed, 14 Feb 2018 14:00:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1518616826; bh=0zL8ShgCa8ox73QztcksRqRCbLfIm6bNCMDqEVkMhNs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AJ9+Mb2SmTqOCIZuncdw0HK4VzqAr9tjO+gx0xUVBbFd9ZrT0mlvrjBA6IGJGhWn4 OxtOfERWkwt8AZd+8Q4J28vFu2G7vrPtI9q+wl4fQDF9IDVotKKA0dlhl5CEnMAsMP Rt5FagSiB9XCpeAauDDpdgOUoIyntebAHE+d59hA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 77FEA60F6D Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilialin@codeaurora.org From: Ilia Lin To: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, sboyd@codeaurora.org Cc: devicetree@vger.kernel.org, robh@kernel.org, mark.rutland@arm.com, will.deacon@arm.com, rnayak@codeaurora.org, ilialin@codeaurora.org, amit.kucheria@linaro.org, nicolas.dechesne@linaro.org, celster@codeaurora.org, tfinkel@codeaurora.org Subject: [PATCH v3 08/10] clk: qcom: Add ACD path to CPU clock driver for msm8996 Date: Wed, 14 Feb 2018 15:59:50 +0200 Message-Id: <1518616792-29028-9-git-send-email-ilialin@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518616792-29028-1-git-send-email-ilialin@codeaurora.org> References: <1518616792-29028-1-git-send-email-ilialin@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The PMUX for each duplex allows for selection of ACD clock source. The DVM (Dynamic Variation Monitor) will flag an error when a voltage droop event is detected. This flagged error enables ACD to provide a div-by-2 clock, sourced from the primary PLL. The duplex will be provided the divided clock until a pre-programmed delay has expired. This change configures ACD during the probe and switches the PMUXes to the ACD clock source. Signed-off-by: Ilia Lin --- drivers/clk/qcom/clk-cpu-8996.c | 110 ++++++++++++++++++++++++++++++++++------ 1 file changed, 95 insertions(+), 15 deletions(-) diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index b0a3b73..1552791 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -17,6 +17,7 @@ #include #include #include "clk-alpha-pll.h" +#include #define VCO(a, b, c) { \ .val = a,\ @@ -29,6 +30,27 @@ #define ACD_INDEX 2 #define ALT_INDEX 3 #define DIV_2_THRESHOLD 600000000 +#define PWRCL_REG_OFFSET 0x0 +#define PERFCL_REG_OFFSET 0x80000 +#define MUX_OFFSET 0x40 +#define ALT_PLL_OFFSET 0x100 +#define SSSCTL_OFFSET 0x160 +/* +APCy_QLL_SSSCTL value: +SACDRCLEN=1 +SSWEN=1 +SSTRTEN=1 +SSTPAPMSWEN=1 +*/ +#define SSSCTL_VAL 0xF + +enum { + APC_BASE, + EFUSE_BASE, + NUM_BASES +}; + +static void __iomem *vbases[NUM_BASES]; static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = { [PLL_OFF_L_VAL] = 0x04, @@ -67,7 +89,7 @@ }; static struct clk_alpha_pll perfcl_pll = { - .offset = 0x80000, + .offset = PERFCL_REG_OFFSET, .regs = prim_pll_regs, .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE, .clkr.hw.init = &(struct clk_init_data){ @@ -79,7 +101,7 @@ }; static struct clk_alpha_pll pwrcl_pll = { - .offset = 0x0, + .offset = PWRCL_REG_OFFSET, .regs = prim_pll_regs, .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE, .clkr.hw.init = &(struct clk_init_data){ @@ -109,7 +131,7 @@ }; static struct clk_alpha_pll perfcl_alt_pll = { - .offset = 0x80100, + .offset = PERFCL_REG_OFFSET + ALT_PLL_OFFSET, .regs = alt_pll_regs, .vco_table = alt_pll_vco_modes, .num_vco = ARRAY_SIZE(alt_pll_vco_modes), @@ -123,7 +145,7 @@ }; static struct clk_alpha_pll pwrcl_alt_pll = { - .offset = 0x100, + .offset = PWRCL_REG_OFFSET + ALT_PLL_OFFSET, .regs = alt_pll_regs, .vco_table = alt_pll_vco_modes, .num_vco = ARRAY_SIZE(alt_pll_vco_modes), @@ -136,6 +158,8 @@ }, }; +static void qcom_cpu_clk_msm8996_acd_init(void); + /* Mux'es */ struct clk_cpu_8996_mux { @@ -218,6 +242,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, switch (event) { case PRE_RATE_CHANGE: ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ALT_INDEX); + qcom_cpu_clk_msm8996_acd_init(); break; case POST_RATE_CHANGE: if (cnd->new_rate < DIV_2_THRESHOLD) @@ -225,7 +250,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, DIV_2_INDEX); else ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, - PLL_INDEX); + ACD_INDEX); break; default: ret = 0; @@ -242,7 +267,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, }; static struct clk_cpu_8996_mux pwrcl_smux = { - .reg = 0x40, + .reg = PWRCL_REG_OFFSET + MUX_OFFSET, .shift = 2, .width = 2, .clkr.hw.init = &(struct clk_init_data) { @@ -258,7 +283,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, }; static struct clk_cpu_8996_mux perfcl_smux = { - .reg = 0x80040, + .reg = PERFCL_REG_OFFSET + MUX_OFFSET, .shift = 2, .width = 2, .clkr.hw.init = &(struct clk_init_data) { @@ -274,7 +299,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, }; static struct clk_cpu_8996_mux pwrcl_pmux = { - .reg = 0x40, + .reg = PWRCL_REG_OFFSET + MUX_OFFSET, .shift = 0, .width = 2, .pll = &pwrcl_pll.clkr.hw, @@ -295,7 +320,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, }; static struct clk_cpu_8996_mux perfcl_pmux = { - .reg = 0x80040, + .reg = PERFCL_REG_OFFSET + MUX_OFFSET, .shift = 0, .width = 2, .pll = &perfcl_pll.clkr.hw, @@ -399,10 +424,64 @@ struct clk_hw_clks { return ret; } +#define CPU_AFINITY_MASK 0xFFF +#define PWRCL_CPU_REG_MASK 0x3 +#define PERFCL_CPU_REG_MASK 0x103 + +/* ACD static settings (HMSS HPG 7.2.2) */ +#define L2ACDCR_REG 0x580ULL +#define L2ACDTD_REG 0x581ULL +#define L2ACDDVMRC_REG 0x584ULL +#define L2ACDSSCR_REG 0x589ULL +#define ACDTD_VAL 0x00006A11 +#define ACDCR_VAL 0x002C5FFD +#define ACDSSCR_VAL 0x00000601 +#define ACDDVMRC_VAL 0x000E0F0F + +static DEFINE_SPINLOCK(acd_lock); + +static void qcom_cpu_clk_msm8996_acd_init(void) +{ + u64 hwid; + unsigned long flags; + + spin_lock_irqsave(&acd_lock, flags); + + hwid = read_cpuid_mpidr() & CPU_AFINITY_MASK; + + /* Program ACD Tunable-Length Delay (TLD) */ + set_l2_indirect_reg(L2ACDTD_REG, ACDTD_VAL); + /* Initial ACD for *this* cluster */ + set_l2_indirect_reg(L2ACDDVMRC_REG, ACDDVMRC_VAL); + /* Program ACD soft start control bits. */ + set_l2_indirect_reg(L2ACDSSCR_REG, ACDSSCR_VAL); + + if (PWRCL_CPU_REG_MASK == (hwid | PWRCL_CPU_REG_MASK)) { + /* Enable Soft Stop/Start */ + if (vbases[APC_BASE]) + writel_relaxed(SSSCTL_VAL, vbases[APC_BASE] + + PWRCL_REG_OFFSET + SSSCTL_OFFSET); + /* Ensure SSSCTL config goes through before enabling ACD. */ + mb(); + /* Program ACD control bits */ + set_l2_indirect_reg(L2ACDCR_REG, ACDCR_VAL); + } + if (PERFCL_CPU_REG_MASK == (hwid | PERFCL_CPU_REG_MASK)) { //else { + /* Program ACD control bits */ + set_l2_indirect_reg(L2ACDCR_REG, ACDCR_VAL); + /* Enable Soft Stop/Start */ + if (vbases[APC_BASE]) + writel_relaxed(SSSCTL_VAL, vbases[APC_BASE] + + PERFCL_REG_OFFSET + SSSCTL_OFFSET); + /* Ensure SSSCTL config goes through before enabling ACD. */ + mb(); + } + + spin_unlock_irqrestore(&acd_lock, flags); +} static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev) { int ret; - void __iomem *base; struct resource *res; struct regmap *regmap_cpu; struct clk_hw_clks *hws; @@ -415,17 +494,17 @@ static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev) if (!data) return -ENOMEM; - hws = devm_kzalloc(dev, sizeof(*hws) + 2 * sizeof(struct clk_hw *), + hws = devm_kzalloc(dev, sizeof(*hws) + 4 * sizeof(struct clk_hw *), GFP_KERNEL); if (!hws) return -ENOMEM; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(dev, res); - if (IS_ERR(base)) - return PTR_ERR(base); + vbases[APC_BASE] = devm_ioremap_resource(dev, res); + if (IS_ERR(vbases[APC_BASE])) + return PTR_ERR(vbases[APC_BASE]); - regmap_cpu = devm_regmap_init_mmio(dev, base, + regmap_cpu = devm_regmap_init_mmio(dev, vbases[APC_BASE], &cpu_msm8996_regmap_config); if (IS_ERR(regmap_cpu)) return PTR_ERR(regmap_cpu); @@ -433,6 +512,7 @@ static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev) ret = qcom_cpu_clk_msm8996_register_clks(dev, hws, regmap_cpu); if (ret) return ret; + qcom_cpu_clk_msm8996_acd_init(); data->hws[0] = &pwrcl_pmux.clkr.hw; data->hws[1] = &perfcl_pmux.clkr.hw;