| Message ID | 1521836461-6515-6-git-send-email-kramasub@codeaurora.org (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
Hi, On Fri, Mar 23, 2018 at 1:21 PM, Karthikeyan Ramasubramanian <kramasub@codeaurora.org> wrote: > + i2c10: i2c@a88000 { > + compatible = "qcom,geni-i2c"; > + reg = <0xa88000 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; > + pinctrl-names = "default", "sleep"; > + pinctrl-0 = <&qup_i2c10_default>; > + pinctrl-1 = <&qup_i2c10_sleep>; > + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; > + clock-frequency = <400000>; Please move the clock-frequency to the board file. Not all devices on all boards will support 400 kHz, so we should be at 100 kHz by default and boards should explicitly say that they support 400 kHz. Other than that things look good to me and you can add my Reviewed-by tag. -Doug -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 17b2fb0..e82c98d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -29,9 +29,27 @@ serial@a84000 { status = "okay"; }; + + i2c@a88000 { + status = "okay"; + }; }; pinctrl@3400000 { + qup-i2c10-default { + pinconf { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup-i2c10-sleep { + pinconf { + pins = "gpio55", "gpio56"; + }; + }; + qup-uart2-default { pinconf_tx { pins = "gpio4"; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 71801b9..a13836f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -196,6 +196,20 @@ interrupt-controller; #interrupt-cells = <2>; + qup_i2c10_default: qup-i2c10-default { + pinmux { + function = "qup10"; + pins = "gpio55", "gpio56"; + }; + }; + + qup_i2c10_sleep: qup-i2c10-sleep { + pinmux { + function = "gpio"; + pins = "gpio55", "gpio56"; + }; + }; + qup_uart2_default: qup-uart2-default { pinmux { function = "qup9"; @@ -310,6 +324,21 @@ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0xa88000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_i2c10_default>; + pinctrl-1 = <&qup_i2c10_sleep>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; }; };
Add one instance of GENI based I2C master controller to enable testing I2C driver using EEPROM slave. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org> --- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 18 ++++++++++++++++++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 29 +++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+)