From patchwork Mon Apr 2 19:06:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sinan Kaya X-Patchwork-Id: 10320241 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B8C7C60116 for ; Mon, 2 Apr 2018 19:08:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A8CA528A4C for ; Mon, 2 Apr 2018 19:08:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9D52228A95; Mon, 2 Apr 2018 19:08:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4D17428A4C for ; Mon, 2 Apr 2018 19:08:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756784AbeDBTGr (ORCPT ); Mon, 2 Apr 2018 15:06:47 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:42292 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756760AbeDBTGn (ORCPT ); Mon, 2 Apr 2018 15:06:43 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 20A0660F90; Mon, 2 Apr 2018 19:06:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522696003; bh=isgr2e9uOaAE0gvUMxDuM+iF0GEDsh79umznqIGPEXk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MLD47bIuC7td5VdcLY9OZTzImDMjC7kJlfAxhkLnE8XQJHAjSoAdd7UwLRJFk9agz 78KDrqjl1FSVWbXg2st1MlKhly8CWc/jiYPE4v/a+t2ZZEE2Ct4vL0QNQsHYW04GHP p6FoIw72Jbk6TWugIzQSMKtIuiSFS9mP5+n/luSg= Received: from drakthul.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: okaya@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 48936601D3; Mon, 2 Apr 2018 19:06:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522696002; bh=isgr2e9uOaAE0gvUMxDuM+iF0GEDsh79umznqIGPEXk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UZb6kJgrxOPbvPr8YSC51hHZxXtwMOXodsXe3QDAmr2DDGGG2eoq+E7jir2pKWlKr HvC/ImMR6XtL20g1oTgBkKmLkZ3G4Kp0UbcLSA05qGBN6jp4ByZI3ZBcAw6GFzBd9Y zysnuRx5XYxLoalVE65ltuBTNGb9b7jsq+hI0pcA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 48936601D3 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: jeffrey.t.kirsher@intel.com Cc: netdev@vger.kernel.org, timur@codeaurora.org, sulrich@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sinan Kaya , intel-wired-lan@lists.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 4/7] igb: eliminate duplicate barriers on weakly-ordered archs Date: Mon, 2 Apr 2018 15:06:27 -0400 Message-Id: <1522695990-31082-5-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522695990-31082-1-git-send-email-okaya@codeaurora.org> References: <1522695990-31082-1-git-send-email-okaya@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP memory-barriers.txt has been updated as follows: "When using writel(), a prior wmb() is not needed to guarantee that the cache coherent memory writes have completed before writing to the MMIO region." Remove old IA-64 comments in the code along with unneeded wmb() in front of writel(). There are places in the code where wmb() has been used as a double barrier for CPU and IO in place of smp_wmb() and wmb() as an optimization. For such places, keep the wmb() but replace the following writel() with writel_relaxed() to have a sequence as wmb() writel_relaxed() mmio_wb() Signed-off-by: Sinan Kaya --- drivers/net/ethernet/intel/igb/igb_main.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c index c1c0bc3..c3f7130 100644 --- a/drivers/net/ethernet/intel/igb/igb_main.c +++ b/drivers/net/ethernet/intel/igb/igb_main.c @@ -5652,11 +5652,7 @@ static int igb_tx_map(struct igb_ring *tx_ring, /* set the timestamp */ first->time_stamp = jiffies; - /* Force memory writes to complete before letting h/w know there - * are new descriptors to fetch. (Only applicable for weak-ordered - * memory model archs, such as IA-64). - * - * We also need this memory barrier to make certain all of the + /* We need this memory barrier to make certain all of the * status bits have been updated before next_to_watch is written. */ wmb(); @@ -5674,7 +5670,7 @@ static int igb_tx_map(struct igb_ring *tx_ring, igb_maybe_stop_tx(tx_ring, DESC_NEEDED); if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { - writel(i, tx_ring->tail); + writel_relaxed(i, tx_ring->tail); /* we need this if more than one processor can write to our tail * at a time, it synchronizes IO on IA64/Altix systems @@ -8073,12 +8069,6 @@ void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) /* update next to alloc since we have filled the ring */ rx_ring->next_to_alloc = i; - /* Force memory writes to complete before letting h/w - * know there are new descriptors to fetch. (Only - * applicable for weak-ordered memory model archs, - * such as IA-64). - */ - wmb(); writel(i, rx_ring->tail); } }