From patchwork Mon Apr 2 19:06:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sinan Kaya X-Patchwork-Id: 10320229 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D35F360532 for ; Mon, 2 Apr 2018 19:07:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C268C2237D for ; Mon, 2 Apr 2018 19:07:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B6F332239C; Mon, 2 Apr 2018 19:07:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2BE7E2239C for ; Mon, 2 Apr 2018 19:07:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756833AbeDBTHS (ORCPT ); Mon, 2 Apr 2018 15:07:18 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:42470 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756804AbeDBTGt (ORCPT ); Mon, 2 Apr 2018 15:06:49 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 20F2B60FA9; Mon, 2 Apr 2018 19:06:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522696008; bh=viAgvX3pfij+MM3HuJ1jMgdsmI2f+6gcVLQwsljC8OA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QXu90+TRO7BGJJFS7jde4SBdGflBtiJ8GjPG+skRya/GF7b7sybIfnmcT5DA9ZM7l d5gWkUX1+UwumrwDYt9FJtzFenbovoTdcdK369elE8F9e2imbkVBP5jEpRSPXqfSaB o83NxY4U/fo3yxBDBuEkyxgqXnae0qN0cIvTUKe8= Received: from drakthul.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: okaya@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 2B61160F6D; Mon, 2 Apr 2018 19:06:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522696007; bh=viAgvX3pfij+MM3HuJ1jMgdsmI2f+6gcVLQwsljC8OA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=h3cgGU4u6eruzUunxnMf2UI06IRDDFb61vCLztlqb/vwCdM1DP3fn3lNwSaT7poad eEPmFLFKoVIH6lArg/HvWpc41iIkZEUuT3OhjRU7kn4o+bTx0AtD/2FW4++jdXKgJG pffVvh45R1ZuGT6B/sQQLHhsP0zV3+DyAK7evueU= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2B61160F6D Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: jeffrey.t.kirsher@intel.com Cc: netdev@vger.kernel.org, timur@codeaurora.org, sulrich@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sinan Kaya , intel-wired-lan@lists.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 7/7] ixgbevf: eliminate duplicate barriers on weakly-ordered archs Date: Mon, 2 Apr 2018 15:06:30 -0400 Message-Id: <1522695990-31082-8-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522695990-31082-1-git-send-email-okaya@codeaurora.org> References: <1522695990-31082-1-git-send-email-okaya@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP memory-barriers.txt has been updated as follows: "When using writel(), a prior wmb() is not needed to guarantee that the cache coherent memory writes have completed before writing to the MMIO region." Remove old IA-64 comments in the code along with unneeded wmb() in front of writel(). There are places in the code where wmb() has been used as a double barrier for CPU and IO in place of smp_wmb() and wmb() as an optimization. For such places, keep the wmb() but replace the following writel() with writel_relaxed() to have a sequence as wmb() writel_relaxed() mmio_wb() Signed-off-by: Sinan Kaya --- drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c | 23 +++++++---------------- 1 file changed, 7 insertions(+), 16 deletions(-) diff --git a/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c b/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c index 757dac6..29b71a7 100644 --- a/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c +++ b/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c @@ -719,12 +719,6 @@ static void ixgbevf_alloc_rx_buffers(struct ixgbevf_ring *rx_ring, /* update next to alloc since we have filled the ring */ rx_ring->next_to_alloc = i; - /* Force memory writes to complete before letting h/w - * know there are new descriptors to fetch. (Only - * applicable for weak-ordered memory model archs, - * such as IA-64). - */ - wmb(); writel(i, rx_ring->tail); } } @@ -1228,10 +1222,6 @@ static int ixgbevf_clean_rx_irq(struct ixgbevf_q_vector *q_vector, struct ixgbevf_ring *xdp_ring = adapter->xdp_ring[rx_ring->queue_index]; - /* Force memory writes to complete before letting h/w - * know there are new descriptors to fetch. - */ - wmb(); writel(xdp_ring->next_to_use, xdp_ring->tail); } @@ -3985,11 +3975,7 @@ static void ixgbevf_tx_map(struct ixgbevf_ring *tx_ring, /* set the timestamp */ first->time_stamp = jiffies; - /* Force memory writes to complete before letting h/w know there - * are new descriptors to fetch. (Only applicable for weak-ordered - * memory model archs, such as IA-64). - * - * We also need this memory barrier (wmb) to make certain all of the + /* We also need this memory barrier (wmb) to make certain all of the * status bits have been updated before next_to_watch is written. */ wmb(); @@ -4004,7 +3990,12 @@ static void ixgbevf_tx_map(struct ixgbevf_ring *tx_ring, tx_ring->next_to_use = i; /* notify HW of packet */ - writel(i, tx_ring->tail); + writel_relaxed(i, tx_ring->tail); + + /* We need this if more than one processor can write to our tail + * at a time, it synchronizes IO on IA64/Altix systems + */ + mmiowb(); return; dma_error: