From patchwork Tue Apr 3 13:22:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Nischal X-Patchwork-Id: 10321071 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8192A60318 for ; Tue, 3 Apr 2018 13:23:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 71DBC28389 for ; Tue, 3 Apr 2018 13:23:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 641B228B8C; Tue, 3 Apr 2018 13:23:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0CED628389 for ; Tue, 3 Apr 2018 13:23:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932314AbeDCNXL (ORCPT ); Tue, 3 Apr 2018 09:23:11 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:53294 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932209AbeDCNXI (ORCPT ); Tue, 3 Apr 2018 09:23:08 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 57CB760807; Tue, 3 Apr 2018 13:23:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522761787; bh=V2Lo+S2xSmXgoZtFfamJK+xWcDlgmJwN+Q5MVtBVCeo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DlTHifDvXcbLe/Q98KA1zt4y3AUszBKMSTGiekHmhK1iSo2SMRyf5XzmmgbAeyZwB RPldQ0BvDwkKaQAhljuFW2nmMSqMCAV6lgja/Fwutx/0prBahShp0jxR0KGOfV9sJ3 GUcCnBGQ5eeVzxbqJJK5UJx3hxiD+FtpomT9boo4= Received: from anischal-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: anischal@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 07BDA607E5; Tue, 3 Apr 2018 13:23:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522761786; bh=V2Lo+S2xSmXgoZtFfamJK+xWcDlgmJwN+Q5MVtBVCeo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=domPh0LwuAlpuMY50ptC4Qrt/mJaorHQ7MQQ4zHv9MOt49XnkKPj9UZb7647AY98J saXWPHaNpuEs4ziDZcZ7+41icNlXODz9cWU+8wPl4jtBAzUus299FQe5cIyNztNXNG gK4rwX6HE0lpLGg1cb9s1wY1OSGepoHikRMfVU8Y= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 07BDA607E5 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=anischal@codeaurora.org From: Amit Nischal To: Stephen Boyd , Michael Turquette Cc: Andy Gross , David Brown , Rajendra Nayak , Odelu Kukatla , Taniya Das , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Amit Nischal Subject: [PATCH v3 1/3] clk: qcom: Clear hardware clock control bit of RCG Date: Tue, 3 Apr 2018 18:52:39 +0530 Message-Id: <1522761761-15262-2-git-send-email-anischal@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522761761-15262-1-git-send-email-anischal@codeaurora.org> References: <1522761761-15262-1-git-send-email-anischal@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For upcoming targets like sdm845, POR value of the hardware clock control bit is set for most of root clocks which needs to be cleared for software to be able to control. For older targets like MSM8996, this bit is reserved bit and having POR value as 0 so this patch will work for the older targets too. So update the configuration mask to take care of the same to clear hardware clock control bit. Signed-off-by: Amit Nischal --- drivers/clk/qcom/clk-rcg2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index bbeaf9c..984de9c 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -42,6 +42,7 @@ #define CFG_MODE_SHIFT 12 #define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT) #define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT) +#define CFG_HW_CLK_CTRL_MASK BIT(20) #define M_REG 0x8 #define N_REG 0xc @@ -276,7 +277,7 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) } mask = BIT(rcg->hid_width) - 1; - mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK; + mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK; cfg = f->pre_div << CFG_SRC_DIV_SHIFT; cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; if (rcg->mnd_width && f->n && (f->m != f->n))