From patchwork Fri Apr 6 18:02:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sinan Kaya X-Patchwork-Id: 10327381 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id F109860545 for ; Fri, 6 Apr 2018 18:03:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DAC4E295DB for ; Fri, 6 Apr 2018 18:03:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CF33E295DD; Fri, 6 Apr 2018 18:03:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 34E71295DB for ; Fri, 6 Apr 2018 18:03:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751897AbeDFSDL (ORCPT ); Fri, 6 Apr 2018 14:03:11 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:50748 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751779AbeDFSCx (ORCPT ); Fri, 6 Apr 2018 14:02:53 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 3623E60850; Fri, 6 Apr 2018 18:02:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1523037773; bh=jOwHyrGjXSLW2VVElUV8XoZGyXfhim/LzT/oa/lqdW8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AajZJukBVOf1+tkEPh8idwo4KdW0Mxpg4aXWbfHKvhIY7Ff7pVDsKZHnRB+SrPz1C RJp/9jeq9swDcScXyyz3jiBb8yqcCZCBoF1AyhQ6xPNn869Jeq6cF55UhgeLBZU+Ho 3yfK4Au+e8vIFct9tuYwsKOpbj62ecl9Z0BciWCQ= Received: from drakthul.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: okaya@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 13861601C4; Fri, 6 Apr 2018 18:02:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1523037772; bh=jOwHyrGjXSLW2VVElUV8XoZGyXfhim/LzT/oa/lqdW8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=C6c5cua0JMlLrWtHiujwE3Op6DrvUe4PDWB5exCsHeJPviZz1XxLQEaFpmVsEq2u2 eAomOKWLTvASjB9Gj+JJfW84MbnOHp7Asx/aAGdzY17D1y6k9yTzuhX7rGYelth+VK wn5eQxPKMSBYP/Azqe7rpxT5QTilbOoQzrsyfDg8= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 13861601C4 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: arnd@arndb.de, timur@codeaurora.org, sulrich@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sinan Kaya , linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] io: change writeX_relaxed() to remove barriers Date: Fri, 6 Apr 2018 14:02:46 -0400 Message-Id: <1523037766-14518-2-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1523037766-14518-1-git-send-email-okaya@codeaurora.org> References: <1523037766-14518-1-git-send-email-okaya@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Now that we hardened writeX() API in asm-generic version, writeX_relaxed() API is violating the rules when writeX_relaxed() == writeX() in the default implementation. The relaxed API shouldn't have any barriers in it and it doesn't provide any ordering with respect to the memory transactions. The only requirement is for writes to be ordered with respect to each other. This is achieved by the volatile in the __raw_writeX() API. Open code the relaxed API and remove any barriers in it. Signed-off-by: Sinan Kaya --- include/asm-generic/io.h | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index fa0975d..f4a1494 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -284,19 +284,35 @@ static inline u64 readq_relaxed(const volatile void __iomem *addr) #endif #ifndef writeb_relaxed -#define writeb_relaxed writeb +#define writeb_relaxed writeb_relaxed +static inline void writeb_relaxed(u8 value, volatile void __iomem *addr) +{ + __raw_writeb(value, addr); +} #endif #ifndef writew_relaxed -#define writew_relaxed writew +#define writew_relaxed writew_relaxed +static inline void writew_relaxed(u16 value, volatile void __iomem *addr) +{ + __raw_writew(cpu_to_le16(value), addr); +} #endif #ifndef writel_relaxed -#define writel_relaxed writel +#define writel_relaxed writel_relaxed +static inline void writel_relaxed(u32 value, volatile void __iomem *addr) +{ + __raw_writel(__cpu_to_le32(value), addr); +} #endif #if defined(writeq) && !defined(writeq_relaxed) -#define writeq_relaxed writeq +#define writeq_relaxed writeq_relaxed +static inline void writeq_relaxed(u64 value, volatile void __iomem *addr) +{ + __raw_writeq(__cpu_to_le64(value), addr); +} #endif /*