From patchwork Tue Apr 17 04:08:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sinan Kaya X-Patchwork-Id: 10344305 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4C7A960542 for ; Tue, 17 Apr 2018 04:09:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3C9B628929 for ; Tue, 17 Apr 2018 04:09:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 30CBB28987; Tue, 17 Apr 2018 04:09:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A368928929 for ; Tue, 17 Apr 2018 04:09:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752604AbeDQEJK (ORCPT ); Tue, 17 Apr 2018 00:09:10 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:47770 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752536AbeDQEJG (ORCPT ); Tue, 17 Apr 2018 00:09:06 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 3A3B260C65; Tue, 17 Apr 2018 04:09:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1523938146; bh=QsXWJ7n5QFEPPozYapfK25KnnzXqw/pvE1CeU+kYbZ0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=e5i9quRlrpThYjMhiLSdZlf6/6tPp5YyGmjKtAFwErgUide7gR+fxfiH6J817iToI LTDm+vWJtNgOOo0uCXfid8EzpMl/e7VZBOZoCB+eP7bOofI2l8OKplYy0LmoR5zSf2 ZTcksutu8N4b48e4KE7/mvwaRXTAxEHcgqlO/LwU= Received: from drakthul.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: okaya@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 3F49660F6E; Tue, 17 Apr 2018 04:09:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1523938145; bh=QsXWJ7n5QFEPPozYapfK25KnnzXqw/pvE1CeU+kYbZ0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QMDxXVjnHPxh1JmgOK2am69dz6w9OEt/BBRjI3NnAqHkM/Kwz3FZLSkiAq58SDDwG 4ZgNPj9zX0ZS4Oolk3lecA0J6fJy/cx/EP7cDUPqBN9OjaqpUQgjk1KqrXjp1sGnIq P1JdcQsSu2FXhk9QPv6qgfTmbQpOiYGjt+lsmQSA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 3F49660F6E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: linux-parisc@vger.kernel.org, arnd@arndb.de, timur@codeaurora.org, sulrich@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sinan Kaya , "James E.J. Bottomley" , Helge Deller , Philippe Ombredanne , Kate Stewart , Thomas Gleixner , Greg Kroah-Hartman , linux-kernel@vger.kernel.org Subject: [PATCH v2 2/2] parisc: define stronger ordering for the default readX() Date: Tue, 17 Apr 2018 00:08:51 -0400 Message-Id: <1523938133-3224-2-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1523938133-3224-1-git-send-email-okaya@codeaurora.org> References: <1523938133-3224-1-git-send-email-okaya@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP parisc architecture seems to be mapping readX() and readX_relaxed() APIs to __raw_readX() API. __raw_readX() API doesn't provide any kind of ordering guarantees. commit 032d59e1cde9 ("io: define stronger ordering for the default readX() implementation") changed asm-generic implementation to use a more conservative approach towards the readX() API. Place a barrier() after the register read so that compiler doesn't optimize across the regiter operation. Signed-off-by: Sinan Kaya --- arch/parisc/include/asm/io.h | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/arch/parisc/include/asm/io.h b/arch/parisc/include/asm/io.h index 2ec6405..e04c4ef 100644 --- a/arch/parisc/include/asm/io.h +++ b/arch/parisc/include/asm/io.h @@ -179,19 +179,34 @@ static inline void __raw_writeq(unsigned long long b, volatile void __iomem *add static inline unsigned char readb(const volatile void __iomem *addr) { - return __raw_readb(addr); + unsigned char ret; + + ret = __raw_readb(addr); + barrier(); + return ret; } static inline unsigned short readw(const volatile void __iomem *addr) { - return le16_to_cpu((__le16 __force) __raw_readw(addr)); + unsigned short ret; + + ret = le16_to_cpu((__le16 __force) __raw_readw(addr)); + barrier(); + return ret; } static inline unsigned int readl(const volatile void __iomem *addr) { - return le32_to_cpu((__le32 __force) __raw_readl(addr)); + unsigned int ret; + ret = le32_to_cpu((__le32 __force) __raw_readl(addr)); + barrier(); + return ret; } static inline unsigned long long readq(const volatile void __iomem *addr) { - return le64_to_cpu((__le64 __force) __raw_readq(addr)); + unsigned long long ret; + + ret = le64_to_cpu((__le64 __force) __raw_readq(addr)); + barrier(); + return ret; } static inline void writeb(unsigned char b, volatile void __iomem *addr)