From patchwork Thu May 17 10:28:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vijay Viswanath X-Patchwork-Id: 10406281 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7D2B1602C2 for ; Thu, 17 May 2018 10:30:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6C2A928A4E for ; Thu, 17 May 2018 10:30:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 606D628A51; Thu, 17 May 2018 10:30:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EA52B28A4E for ; Thu, 17 May 2018 10:30:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751644AbeEQK3g (ORCPT ); Thu, 17 May 2018 06:29:36 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:51228 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751626AbeEQK3d (ORCPT ); Thu, 17 May 2018 06:29:33 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id DDF5060D81; Thu, 17 May 2018 10:29:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1526552972; bh=OFXSAdJdDmqxG0ozXYmUiSW6nkkFN2zBv6j5ASBPlfA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GEWC992WpGkB0DIOzsTWP8MZ516T0aFupkU27kJJ6e1syekHTO0EFkBDn13gjoXxo JEaxpd9PfOTaoYWJPU4oOqMSJWfK4Pu0Kh78YWj1JyHLiiYwYWwpXGOZqUokmWZ+OH MVaf576id7Y4JYuYyoHtu758QJ0KG7sPXU2a8Vwc= Received: from hydcbspbld03.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: vviswana@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id C6AB160F61; Thu, 17 May 2018 10:29:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1526552971; bh=OFXSAdJdDmqxG0ozXYmUiSW6nkkFN2zBv6j5ASBPlfA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mwIUxf+QDa+2JQ+fRAjAxDEwhKG9oieZurmyfts8hkttgmkMnfYD/INuYPrC7+AU8 8Zk8/boVY5cEx1nFGnLp7P3iNns/I6Qpz+eS4DfzXD7Pu2KYYS6ek+8zX0t1IrV8Go KyIgKhJ2Vom5+5PTOu6Poha163GSl5JjXQMhh5cY= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C6AB160F61 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vviswana@codeaurora.org From: Vijay Viswanath To: adrian.hunter@intel.com, ulf.hansson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, shawn.lin@rock-chips.com, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org, devicetree@vger.kernel.org, asutoshd@codeaurora.org, stummala@codeaurora.org, venkatg@codeaurora.org, jeremymc@redhat.com, vviswana@codeaurora.org, bjorn.andersson@linaro.org, riteshh@codeaurora.org, vbadigan@codeaurora.org, dianders@google.com, sayalil@codeaurora.org Subject: [PATCH V1 2/3] mmc: sdhci-msm: Add msm version specific ops and data structures Date: Thu, 17 May 2018 15:58:57 +0530 Message-Id: <1526552938-21292-3-git-send-email-vviswana@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1526552938-21292-1-git-send-email-vviswana@codeaurora.org> References: <1526552938-21292-1-git-send-email-vviswana@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In addition to offsets of certain registers changing, the registers in core_mem have been shifted to HC mem as well. To access these registers, define msm version specific functions. These functions can be loaded into the function pointers at the time of probe based on the msm version detected. Also defind new data structure to hold version specific Ops and register addresses. Signed-off-by: Sayali Lokhande Signed-off-by: Vijay Viswanath --- drivers/mmc/host/sdhci-msm.c | 112 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 2524455..bb2bb59 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -226,6 +226,25 @@ struct sdhci_msm_offset { .core_ddr_config_2 = 0x1BC, }; +struct sdhci_msm_variant_ops { + u8 (*msm_readb_relaxed)(struct sdhci_host *host, u32 offset); + u32 (*msm_readl_relaxed)(struct sdhci_host *host, u32 offset); + void (*msm_writeb_relaxed)(u8 val, struct sdhci_host *host, u32 offset); + void (*msm_writel_relaxed)(u32 val, struct sdhci_host *host, + u32 offset); +}; + +/* + * From V5, register spaces have changed. Wrap this info in a structure + * and choose the data_structure based on version info mentioned in DT. + */ +struct sdhci_msm_variant_info { + bool mci_removed; + const struct sdhci_msm_variant_ops *var_ops; + const struct sdhci_msm_offset *offset; +}; + + struct sdhci_msm_host { struct platform_device *pdev; void __iomem *core_mem; /* MSM SDCC mapped address */ @@ -245,8 +264,75 @@ struct sdhci_msm_host { wait_queue_head_t pwr_irq_wait; bool pwr_irq_flag; u32 caps_0; + bool mci_removed; + const struct sdhci_msm_variant_ops *var_ops; + const struct sdhci_msm_offset *offset; }; +/* + * APIs to read/write to vendor specific registers which were there in the + * core_mem region before MCI was removed. + */ +static u8 sdhci_msm_mci_variant_readb_relaxed(struct sdhci_host *host, + u32 offset) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); + + return readb_relaxed(msm_host->core_mem + offset); +} + +static u8 sdhci_msm_v5_variant_readb_relaxed(struct sdhci_host *host, + u32 offset) +{ + return readb_relaxed(host->ioaddr + offset); +} + +static u32 sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host *host, + u32 offset) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); + + return readl_relaxed(msm_host->core_mem + offset); +} + +static u32 sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host *host, + u32 offset) +{ + return readl_relaxed(host->ioaddr + offset); +} + +static void sdhci_msm_mci_variant_writeb_relaxed(u8 val, + struct sdhci_host *host, u32 offset) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); + + writeb_relaxed(val, msm_host->core_mem + offset); +} + +static void sdhci_msm_v5_variant_writeb_relaxed(u8 val, struct sdhci_host *host, + u32 offset) +{ + writeb_relaxed(val, host->ioaddr + offset); +} + +static void sdhci_msm_mci_variant_writel_relaxed(u32 val, + struct sdhci_host *host, u32 offset) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); + + writel_relaxed(val, msm_host->core_mem + offset); +} + +static void sdhci_msm_v5_variant_writel_relaxed(u32 val, struct sdhci_host *host, + u32 offset) +{ + writel_relaxed(val, host->ioaddr + offset); +} + static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host, unsigned int clock) { @@ -1481,6 +1567,32 @@ static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host) pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps); } +static const struct sdhci_msm_variant_ops mci_var_ops = { + .msm_readb_relaxed = sdhci_msm_mci_variant_readb_relaxed, + .msm_readl_relaxed = sdhci_msm_mci_variant_readl_relaxed, + .msm_writeb_relaxed = sdhci_msm_mci_variant_writeb_relaxed, + .msm_writel_relaxed = sdhci_msm_mci_variant_writel_relaxed, +}; + +static const struct sdhci_msm_variant_ops v5_var_ops = { + .msm_readb_relaxed = sdhci_msm_v5_variant_readb_relaxed, + .msm_readl_relaxed = sdhci_msm_v5_variant_readl_relaxed, + .msm_writeb_relaxed = sdhci_msm_v5_variant_writeb_relaxed, + .msm_writel_relaxed = sdhci_msm_v5_variant_writel_relaxed, +}; + +static const struct sdhci_msm_variant_info sdhci_msm_mci_var = { + .mci_removed = 0, + .var_ops = &mci_var_ops, + .offset = &sdhci_msm_mci_offset, +}; + +static const struct sdhci_msm_variant_info sdhci_msm_v5_var = { + .mci_removed = 1, + .var_ops = &v5_var_ops, + .offset = &sdhci_msm_v5_offset, +}; + static const struct of_device_id sdhci_msm_dt_match[] = { { .compatible = "qcom,sdhci-msm-v4" }, {},