From patchwork Wed May 23 19:30:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeykumar Sankaran X-Patchwork-Id: 10422191 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AC5BF60545 for ; Wed, 23 May 2018 19:31:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9E0F1291B6 for ; Wed, 23 May 2018 19:31:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 92ABC291BF; Wed, 23 May 2018 19:31:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D5774291BB for ; Wed, 23 May 2018 19:31:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934277AbeEWTbb (ORCPT ); Wed, 23 May 2018 15:31:31 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:41684 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934448AbeEWTbV (ORCPT ); Wed, 23 May 2018 15:31:21 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 4211B60F71; Wed, 23 May 2018 19:31:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527103880; bh=fjCU8jcicjS4Qls/8dXHuIjhZGFqvfyW8/NVr7r4ul0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=X3eNvW2K+1g5Ti/BXfjN1fKe/3uKFhpJeUSJieMUHa+aqzCQKKv9oMTZ5CfFTudCa OpZZj0JPTOaN9whksJcJ2DVZc9RALw2k2tXd/BFQRtO8bYeRuFF9NzKGifB+KY08Lz SF4HzK1kxh2jica0WHu6rkTv+TEEq4do3proFYu4= Received: from jeykumar-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jsanka@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 537B86090E; Wed, 23 May 2018 19:31:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527103873; bh=fjCU8jcicjS4Qls/8dXHuIjhZGFqvfyW8/NVr7r4ul0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=h02hJhB01T+mn2JgqAaHrnVBBaC5A3hTc5iaJ0A5johMkRaM1FwIIPiKMVu6mqAkv CF1MmzdN32ZpCNd1Ey9mFtHIETvZMgIojNBeaybAhtX7q1VYRCRyKpdfcK5dXQMzwz HjVYj3Fa35iJeF0KsA552UB5AZakcQlrkZREmwSw= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 537B86090E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jsanka@codeaurora.org From: Jeykumar Sankaran To: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Cc: Jeykumar Sankaran , seanpaul@chromium.org, robdclark@gmail.com, hoegsberg@google.com Subject: [DPU PATCH 4/7] drm/msm/dpu: switch to drm zpos property Date: Wed, 23 May 2018 12:30:59 -0700 Message-Id: <1527103862-13934-5-git-send-email-jsanka@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1527103862-13934-1-git-send-email-jsanka@codeaurora.org> References: <1527103862-13934-1-git-send-email-jsanka@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Replace custom plane zpos property with drm core zpos property. CRTC relies on the normalized zpos values to configure blend stages of each plane. Signed-off-by: Jeykumar Sankaran --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 36 +------------------------------ drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 18 +++++++++++++--- 2 files changed, 16 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index d439a9e..a0b702f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -2631,24 +2631,6 @@ struct plane_state { u32 pipe_id; }; -static int pstate_cmp(const void *a, const void *b) -{ - struct plane_state *pa = (struct plane_state *)a; - struct plane_state *pb = (struct plane_state *)b; - int rc = 0; - int pa_zpos, pb_zpos; - - pa_zpos = dpu_plane_get_property(pa->dpu_pstate, PLANE_PROP_ZPOS); - pb_zpos = dpu_plane_get_property(pb->dpu_pstate, PLANE_PROP_ZPOS); - - if (pa_zpos != pb_zpos) - rc = pa_zpos - pb_zpos; - else - rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x; - - return rc; -} - static int dpu_crtc_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) { @@ -2714,8 +2696,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate); pstates[cnt].drm_pstate = pstate; - pstates[cnt].stage = dpu_plane_get_property( - pstates[cnt].dpu_pstate, PLANE_PROP_ZPOS); + pstates[cnt].stage = pstate->normalized_zpos; pstates[cnt].pipe_id = dpu_plane_pipe(plane); /* check dim layer stage with every plane */ @@ -2771,21 +2752,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, } } - /* assign mixer stages based on sorted zpos property */ - sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL); - - if (!dpu_is_custom_client()) { - int stage_old = pstates[0].stage; - - z_pos = 0; - for (i = 0; i < cnt; i++) { - if (stage_old != pstates[i].stage) - ++z_pos; - stage_old = pstates[i].stage; - pstates[i].stage = z_pos; - } - } - z_pos = -1; for (i = 0; i < cnt; i++) { /* reset counts at every new blend stage */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index b033653..28735c8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -59,6 +59,7 @@ #define DPU_NAME_SIZE 12 #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) +#define DPU_ZPOS_MAX 255 /* multirect rect index */ enum { @@ -1518,9 +1519,6 @@ static void _dpu_plane_install_properties(struct drm_plane *plane, /* reserve zpos == 0 for primary planes */ zpos_def = drm_plane_index(plane) + 1; } - - msm_property_install_range(&pdpu->property_info, "zpos", - 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS); } static int dpu_plane_atomic_set_property(struct drm_plane *plane, @@ -1958,6 +1956,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, struct msm_drm_private *priv; struct dpu_kms *kms; enum drm_plane_type type; + int zpos_max = DPU_ZPOS_MAX; int ret = -EINVAL; if (!dev) { @@ -2049,6 +2048,19 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, if (ret) goto clean_sspp; + pdpu->catalog = kms->catalog; + + if (kms->catalog->mixer_count && + kms->catalog->mixer[0].sblk->maxblendstages) { + zpos_max = kms->catalog->mixer[0].sblk->maxblendstages - 1; + if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1) + zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1; + } + + ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max); + if (ret) + DPU_ERROR("failed to install zpos property, rc = %d\n", ret); + /* success! finalize initialization */ drm_plane_helper_add(plane, &dpu_plane_helper_funcs);