From patchwork Fri May 25 12:21:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhishek Sahu X-Patchwork-Id: 10427225 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B4029602D8 for ; Fri, 25 May 2018 12:23:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 973C128674 for ; Fri, 25 May 2018 12:23:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8B948286C5; Fri, 25 May 2018 12:23:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F248028674 for ; Fri, 25 May 2018 12:23:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S967118AbeEYMXK (ORCPT ); Fri, 25 May 2018 08:23:10 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:49874 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S967001AbeEYMXH (ORCPT ); Fri, 25 May 2018 08:23:07 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id B918C60F5F; Fri, 25 May 2018 12:23:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527250986; bh=O1p0FEPbiOgvfwOsm3ZAZ0vd5pFxge8CC6gTpDWzQw8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=c9V6m5pijuNClo7ZJiQCOhM9/eY9sjjW8RXqsgm5Mf570gxv417VU8HpXbhI14J83 JoH36TGvAFSqrmHH8a+1K1jU7ySjTm+07ODdGG9abncvj/hwj/V+zclV9QJtrB7WW/ Hv4pwYDbIpkYZ4Isefm2WDqNYVk591KXmgcqQ59k= Received: from absahu-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: absahu@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 35BCF60117; Fri, 25 May 2018 12:23:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527250985; bh=O1p0FEPbiOgvfwOsm3ZAZ0vd5pFxge8CC6gTpDWzQw8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NJENNAxoQ5q0QQZE8rso7N7MMR5+TAk/G889867R+R0nbj/HvDok1ABFSfYAiYzAu LDIlJo/YaihbvF6EFddd2bYoLFwum40m9GQ+UDamxehRG0ipgWqZNMCoIJvgeY93Pe jjqmcSJzAlqkHou4JHB6mdbN15mCN5WoAopz1UzY= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 35BCF60117 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=absahu@codeaurora.org From: Abhishek Sahu To: Boris Brezillon Cc: David Woodhouse , Brian Norris , Marek Vasut , Richard Weinberger , Cyrille Pitchen , Miquel Raynal , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Andy Gross , Archit Taneja , Abhishek Sahu Subject: [PATCH v3 15/16] mtd: rawnand: qcom: helper function for raw read Date: Fri, 25 May 2018 17:51:43 +0530 Message-Id: <1527250904-21988-16-git-send-email-absahu@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1527250904-21988-1-git-send-email-absahu@codeaurora.org> References: <1527250904-21988-1-git-send-email-absahu@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch does minor code reorganization for raw reads. Currently the raw read is required for complete page but for subsequent patches related with erased codeword bit flips detection, only few CW should be read. So, this patch adds helper function and introduces the read CW bitmask which specifies which CW reads are required in complete page. Signed-off-by: Abhishek Sahu --- * Changes from v2: NONE * Changes from v1: 1. Included more detail in function comment drivers/mtd/nand/raw/qcom_nandc.c | 197 ++++++++++++++++++++++++-------------- 1 file changed, 123 insertions(+), 74 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 87f900e..34143a4 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -1588,6 +1588,127 @@ static int check_flash_errors(struct qcom_nand_host *host, int cw_cnt) } /* + * Helper to perform the page raw read operation. The read_cw_mask will be + * used to specify the codewords (CW) for which the data should be read. The + * single page contains multiple CW. + * + * Normally other NAND controllers store the data in main area and + * ecc bytes in OOB area. So, if page size is 2048+64 then 2048 + * data bytes will go in main area followed by ECC bytes. The QCOM NAND + * controller follows different layout in which the data+OOB is internally + * divided in 528/532 bytes CW and each CW contains 516 bytes followed by + * ECC parity bytes for that CW. By this, 4 available OOB bytes per CW + * will also be protected with ECC. + * + * For each CW read, following are the 2 steps: + * 1. Read the codeword bytes from NAND chip to NAND controller internal HW + * buffer. + * 2. Copy all these bytes from this HW buffer to actual buffer. + * + * Sometime, only few CW data is required in complete page. The read_cw_mask + * specifies which CW in a page needs to be read. Start address will be + * determined with this CW mask to skip unnecessary data copy from NAND + * flash device. Then, actual data copy from NAND controller HW internal buffer + * to data buffer will be done only for the CWs, which have the mask set. + */ +static int +nandc_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, + u8 *data_buf, u8 *oob_buf, + int page, unsigned long read_cw_mask) +{ + struct qcom_nand_host *host = to_qcom_nand_host(chip); + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); + struct nand_ecc_ctrl *ecc = &chip->ecc; + int i, ret; + int read_loc, start_step, last_step; + + nand_read_page_op(chip, page, 0, NULL, 0); + + host->use_ecc = false; + start_step = ffs(read_cw_mask) - 1; + last_step = fls(read_cw_mask); + + clear_bam_transaction(nandc); + set_address(host, host->cw_size * start_step, page); + update_rw_regs(host, last_step - start_step, true); + config_nand_page_read(nandc); + + for (i = start_step; i < last_step; i++) { + int data_size1, data_size2, oob_size1, oob_size2; + int reg_off = FLASH_BUF_ACC; + + data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); + oob_size1 = host->bbm_size; + + if (i == (ecc->steps - 1)) { + data_size2 = ecc->size - data_size1 - + ((ecc->steps - 1) << 2); + oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw + + host->spare_bytes; + } else { + data_size2 = host->cw_data - data_size1; + oob_size2 = host->ecc_bytes_hw + host->spare_bytes; + } + + /* + * Don't perform actual data copy from NAND controller internal + * HW buffer to data buffer through DMA for this codeword. + */ + if (!(read_cw_mask & BIT(i))) { + if (nandc->props->is_bam) + nandc_set_read_loc(nandc, 0, 0, 0, 1); + + config_nand_cw_read(nandc, false); + + data_buf += data_size1 + data_size2; + oob_buf += oob_size1 + oob_size2; + + continue; + } + + if (nandc->props->is_bam) { + read_loc = 0; + nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0); + read_loc += data_size1; + + nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0); + read_loc += oob_size1; + + nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0); + read_loc += data_size2; + + nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1); + } + + config_nand_cw_read(nandc, false); + + read_data_dma(nandc, reg_off, data_buf, data_size1, 0); + reg_off += data_size1; + data_buf += data_size1; + + read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0); + reg_off += oob_size1; + oob_buf += oob_size1; + + read_data_dma(nandc, reg_off, data_buf, data_size2, 0); + reg_off += data_size2; + data_buf += data_size2; + + read_data_dma(nandc, reg_off, oob_buf, oob_size2, 0); + oob_buf += oob_size2; + } + + ret = submit_descs(nandc); + free_descs(nandc); + if (ret) { + dev_err(nandc->dev, "failure to read raw page\n"); + return ret; + } + + return check_flash_errors(host, ecc->steps); +} + +/* * reads back status registers set by the controller to notify page read * errors. this is equivalent to what 'ecc->correct()' would do. */ @@ -1815,80 +1936,8 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int oob_required, int page) { - struct qcom_nand_host *host = to_qcom_nand_host(chip); - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - u8 *data_buf, *oob_buf; - struct nand_ecc_ctrl *ecc = &chip->ecc; - int i, ret; - int read_loc; - - nand_read_page_op(chip, page, 0, NULL, 0); - data_buf = buf; - oob_buf = chip->oob_poi; - - host->use_ecc = false; - - clear_bam_transaction(nandc); - update_rw_regs(host, ecc->steps, true); - config_nand_page_read(nandc); - - for (i = 0; i < ecc->steps; i++) { - int data_size1, data_size2, oob_size1, oob_size2; - int reg_off = FLASH_BUF_ACC; - - data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); - oob_size1 = host->bbm_size; - - if (i == (ecc->steps - 1)) { - data_size2 = ecc->size - data_size1 - - ((ecc->steps - 1) << 2); - oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw + - host->spare_bytes; - } else { - data_size2 = host->cw_data - data_size1; - oob_size2 = host->ecc_bytes_hw + host->spare_bytes; - } - - if (nandc->props->is_bam) { - read_loc = 0; - nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0); - read_loc += data_size1; - - nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0); - read_loc += oob_size1; - - nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0); - read_loc += data_size2; - - nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1); - } - - config_nand_cw_read(nandc, false); - - read_data_dma(nandc, reg_off, data_buf, data_size1, 0); - reg_off += data_size1; - data_buf += data_size1; - - read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0); - reg_off += oob_size1; - oob_buf += oob_size1; - - read_data_dma(nandc, reg_off, data_buf, data_size2, 0); - reg_off += data_size2; - data_buf += data_size2; - - read_data_dma(nandc, reg_off, oob_buf, oob_size2, 0); - oob_buf += oob_size2; - } - - ret = submit_descs(nandc); - free_descs(nandc); - if (ret) { - dev_err(nandc->dev, "failure to read raw page\n"); - return ret; - } - - return check_flash_errors(host, ecc->steps); + return nandc_read_page_raw(mtd, chip, buf, chip->oob_poi, page, + BIT(chip->ecc.steps) - 1); } /* implements ecc->read_oob() */