From patchwork Wed May 30 03:19:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sinan Kaya X-Patchwork-Id: 10437579 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1D980601D3 for ; Wed, 30 May 2018 03:20:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0CD472858A for ; Wed, 30 May 2018 03:20:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0097828744; Wed, 30 May 2018 03:20:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CA15E2858A for ; Wed, 30 May 2018 03:20:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935478AbeE3DUD (ORCPT ); Tue, 29 May 2018 23:20:03 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:54496 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935420AbeE3DUB (ORCPT ); Tue, 29 May 2018 23:20:01 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id D3BBD60708; Wed, 30 May 2018 03:20:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527650400; bh=WHrbPoV80t2S9FvOyOnH0c9jo1eUPSwqCm/13BOIp7Q=; h=From:To:Cc:Subject:Date:From; b=ngfJBkypfZ1OAslviMx+O1+S9fRIJkfK1NEK9tzgI/GmzA8nML+f0zZwUWknWvsyo +ATBGBxwVbl8VKoFxrVFIU3F+6VYKm8NxanyXHaHELYIL0V3CoUPd63ptOHmUSxgCJ D1DDKc/SeAVsZpd5QDWah3qiBMzv80KXp8W8Nqqw= Received: from drakthul.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: okaya@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 87AD360261; Wed, 30 May 2018 03:19:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527650398; bh=WHrbPoV80t2S9FvOyOnH0c9jo1eUPSwqCm/13BOIp7Q=; h=From:To:Cc:Subject:Date:From; b=PytGFCFiGsKg0Hf2cb/wyBH3kY36WX2HoJXRRuMyco+Za2rvhFhYAOf42qkV3tH+B njDXwJwrXBK+C7M+faRPnUoQK1SbIdVsV8Kbd3jzYsB1mBB3GL/qhHpSXKgAmdPfkY IAljWE4esNjNgmKOGw5CyOyuS3AwObvF+pGaOy0c= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 87AD360261 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: linux-pci@vger.kernel.org, timur@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sinan Kaya , Jonathan Corbet , Bjorn Helgaas , Thomas Gleixner , Ingo Molnar , Christoffer Dall , "Paul E. McKenney" , Marc Zyngier , Kai-Heng Feng , Thymo van Beers , Frederic Weisbecker , Konrad Rzeszutek Wilk , Greg Kroah-Hartman , David Rientjes , "Rafael J. Wysocki" , Keith Busch , Dongdong Liu , Frederick Lawler , Oza Pawandeep , Gabriele Paoloni , linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-kernel@vger.kernel.org (open list) Subject: [PATCH] PCI: Add pci=safemode option Date: Tue, 29 May 2018 23:19:41 -0400 Message-Id: <1527650389-31575-1-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adding pci=safemode kernel command line parameter to turn off all PCI Express service driver as well as all optional PCIe features such as LTR, Extended tags, Relaxed Ordering etc. Also setting MPS configuration to PCIE_BUS_SAFE so that MPS and MRRS can be reconfigured with by the kernel in case BIOS hands off a broken configuration. Signed-off-by: Sinan Kaya --- Documentation/admin-guide/kernel-parameters.txt | 2 ++ drivers/pci/pci.c | 7 +++++++ drivers/pci/pci.h | 2 ++ drivers/pci/pcie/portdrv_core.c | 2 +- drivers/pci/probe.c | 6 ++++++ 5 files changed, 18 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 641ec9c..247adbb 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -3153,6 +3153,8 @@ noari do not use PCIe ARI. noats [PCIE, Intel-IOMMU, AMD-IOMMU] do not use PCIe ATS (and IOMMU device IOTLB). + safemode turns of all optinal PCI features. Useful + for bringup/troubleshooting. pcie_scan_all Scan all possible PCIe devices. Otherwise we only look for one device below a PCIe downstream port. diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index d27f771..11f0282 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -115,6 +115,9 @@ static bool pcie_ari_disabled; /* If set, the PCIe ATS capability will not be used. */ static bool pcie_ats_disabled; +/* If set, disables most of the optional PCI features */ +bool pci_safe_mode; + bool pci_ats_disabled(void) { return pcie_ats_disabled; @@ -5845,6 +5848,10 @@ static int __init pci_setup(char *str) if (*str && (str = pcibios_setup(str)) && *str) { if (!strcmp(str, "nomsi")) { pci_no_msi(); + } else if (!strncmp(str, "safemode", 8)) { + pr_info("PCI: safe mode with minimum features\n"); + pci_safe_mode = true; + pcie_bus_config = PCIE_BUS_SAFE; } else if (!strncmp(str, "noats", 5)) { pr_info("PCIe: ATS is disabled\n"); pcie_ats_disabled = true; diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index c358e7a0..4517bcd 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -8,6 +8,8 @@ extern const unsigned char pcie_link_speed[]; +extern bool pci_safe_mode; + bool pcie_cap_has_lnkctl(const struct pci_dev *dev); /* Functions internal to the PCI core code */ diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index a5b3b3a..9fe4ed6 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -311,7 +311,7 @@ int pcie_port_device_register(struct pci_dev *dev) /* Get and check PCI Express port services */ capabilities = get_port_device_capability(dev); - if (!capabilities) + if (!capabilities || pci_safe_mode) return 0; pci_set_master(dev); diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 3840207..295b79c 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2047,6 +2047,9 @@ static void pci_configure_device(struct pci_dev *dev) struct hotplug_params hpp; int ret; + if (pci_safe_mode) + return; + pci_configure_mps(dev); pci_configure_extended_tags(dev, NULL); pci_configure_relaxed_ordering(dev); @@ -2213,6 +2216,9 @@ static void pci_init_capabilities(struct pci_dev *dev) /* Setup MSI caps & disable MSI/MSI-X interrupts */ pci_msi_setup_pci_dev(dev); + if (pci_safe_mode) + return; + /* Buffers for saving PCIe and PCI-X capabilities */ pci_allocate_cap_save_buffers(dev);