From patchwork Wed May 30 14:49:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajesh Yadav X-Patchwork-Id: 10439165 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9BADA60327 for ; Wed, 30 May 2018 14:51:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8960E290DA for ; Wed, 30 May 2018 14:51:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 834A62902A; Wed, 30 May 2018 14:51:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F00A1290DA for ; Wed, 30 May 2018 14:50:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753474AbeE3Ouq (ORCPT ); Wed, 30 May 2018 10:50:46 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:57074 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753432AbeE3Ouo (ORCPT ); Wed, 30 May 2018 10:50:44 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id EF2D660646; Wed, 30 May 2018 14:50:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527691844; bh=YjsByR2sDIK/HDLwgu7eatZ7GpK3mGzRxh0gumYeQBY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XIoaeWReJ5GcN/nK53q/yEBqKVZAVC7gYFuQmF0QivAtjBN99wDZtL8cZFFiMBWr/ mx+VoXFjAUfTic/0tJJQZpz4KbyCzqAqRLvSjb/C462Fk4I6whSVdoBM0n8Ile3/ed SWVl60YHYjZSeXu/whStVlMn5a8TEDfgZ5qRVKiQ= Received: from ryadav-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ryadav@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id E30D36074F; Wed, 30 May 2018 14:50:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527691839; bh=YjsByR2sDIK/HDLwgu7eatZ7GpK3mGzRxh0gumYeQBY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IMzPKKmOzrvQ+1Zqe02oIULYj/AiRISDZdm75iALUqpLHC334wT/gnjykLvgzMrOu g3qYPYj6tDca//OXm1rp73nuJdEvG1cA1JQRRuHCiakq8Q48ijcs+p9nx0FwBeJL/U 6xm8MYOQp3o3+3is8obGdl4cHQB2m03I6zjgTjdw= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E30D36074F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ryadav@codeaurora.org From: Rajesh Yadav To: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: Rajesh Yadav , robdclark@gmail.com, seanpaul@chromium.org, hoegsberg@chromium.org Subject: [DPU PATCH 07/11] drm/msm/dpu: remove dt parsing logic for bus_scale config Date: Wed, 30 May 2018 20:19:44 +0530 Message-Id: <1527691788-9350-8-git-send-email-ryadav@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1527691788-9350-1-git-send-email-ryadav@codeaurora.org> References: <1527691788-9350-1-git-send-email-ryadav@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Bus scale config related dt-bindings are removed. Add bus_scale config in driver instead. Signed-off-by: Rajesh Yadav --- drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 254 +++++++++++++++-------- 1 file changed, 167 insertions(+), 87 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c index bdf18de..24c3274 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c @@ -20,15 +20,137 @@ #include #include #include -#ifdef CONFIG_QCOM_BUS_SCALING -#include -#include -#endif #include #include "dpu_power_handle.h" #include "dpu_trace.h" +#ifdef CONFIG_QCOM_BUS_SCALING +#include +#include + +#define DPU_BUS_VECTOR_ENTRY(src_val, dst_val, ab_val, ib_val) \ + { \ + .src = src_val, \ + .dst = dst_val, \ + .ab = (ab_val), \ + .ib = (ib_val), \ + } + +static struct msm_bus_vectors dpu_reg_bus_vectors[] = { + DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_FIRST, + MSM_BUS_SLAVE_DISPLAY_CFG, 0, 0), + DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_FIRST, + MSM_BUS_SLAVE_DISPLAY_CFG, 0, 76800000), + DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_FIRST, + MSM_BUS_SLAVE_DISPLAY_CFG, 0, 150000000), + DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_FIRST, + MSM_BUS_SLAVE_DISPLAY_CFG, 0, 300000000), +}; + +static struct msm_bus_paths dpu_reg_bus_usecases[] = { { + .num_paths = 1, + .vectors = &dpu_reg_bus_vectors[0], +}, { + .num_paths = 1, + .vectors = &dpu_reg_bus_vectors[1], +}, { + .num_paths = 1, + .vectors = &dpu_reg_bus_vectors[2], +}, { + .num_paths = 1, + .vectors = &dpu_reg_bus_vectors[3], +} }; + +static struct msm_bus_scale_pdata dpu_reg_bus_scale_table = { + .usecase = dpu_reg_bus_usecases, + .num_usecases = ARRAY_SIZE(dpu_reg_bus_usecases), + .name = "mdss_reg", +}; + +static struct msm_bus_vectors dpu_data_bus_vectors[] = { + DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_MDP_PORT0, + MSM_BUS_SLAVE_MNOC_HF_MEM_NOC, 0, 0), + DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_MDP_PORT1, + MSM_BUS_SLAVE_MNOC_HF_MEM_NOC, 0, 0), + DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_MDP_PORT0, + MSM_BUS_SLAVE_MNOC_HF_MEM_NOC, 0, 6400000000), + DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_MDP_PORT1, + MSM_BUS_SLAVE_MNOC_HF_MEM_NOC, 0, 6400000000), + DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_MDP_PORT0, + MSM_BUS_SLAVE_MNOC_HF_MEM_NOC, 0, 6400000000), + DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_MDP_PORT1, + MSM_BUS_SLAVE_MNOC_HF_MEM_NOC, 0, 6400000000), +}; + +static struct msm_bus_paths dpu_data_bus_usecases[] = { { + .num_paths = 2, + .vectors = &dpu_data_bus_vectors[0], +}, { + .num_paths = 2, + .vectors = &dpu_data_bus_vectors[2], +}, { + .num_paths = 2, + .vectors = &dpu_data_bus_vectors[4], +} }; + +static struct msm_bus_scale_pdata dpu_data_bus_scale_table = { + .usecase = dpu_data_bus_usecases, + .num_usecases = ARRAY_SIZE(dpu_data_bus_usecases), + .name = "mdss_mnoc", +}; + +static struct msm_bus_vectors dpu_llcc_bus_vectors[] = { + DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_MNOC_HF_MEM_NOC, + MSM_BUS_SLAVE_LLCC, 0, 0), + DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_MNOC_HF_MEM_NOC, + MSM_BUS_SLAVE_LLCC, 0, 6400000000), + DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_MNOC_HF_MEM_NOC, + MSM_BUS_SLAVE_LLCC, 0, 6400000000), +}; + +static struct msm_bus_paths dpu_llcc_bus_usecases[] = { { + .num_paths = 1, + .vectors = &dpu_llcc_bus_vectors[0], +}, { + .num_paths = 1, + .vectors = &dpu_llcc_bus_vectors[1], +}, { + .num_paths = 1, + .vectors = &dpu_llcc_bus_vectors[2], +} }; +static struct msm_bus_scale_pdata dpu_llcc_bus_scale_table = { + .usecase = dpu_llcc_bus_usecases, + .num_usecases = ARRAY_SIZE(dpu_llcc_bus_usecases), + .name = "mdss_llcc", +}; + +static struct msm_bus_vectors dpu_ebi_bus_vectors[] = { + DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_LLCC, + MSM_BUS_SLAVE_EBI_CH0, 0, 0), + DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_LLCC, + MSM_BUS_SLAVE_EBI_CH0, 0, 6400000000), + DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_LLCC, + MSM_BUS_SLAVE_EBI_CH0, 0, 6400000000), +}; + +static struct msm_bus_paths dpu_ebi_bus_usecases[] = { { + .num_paths = 1, + .vectors = &dpu_ebi_bus_vectors[0], +}, { + .num_paths = 1, + .vectors = &dpu_ebi_bus_vectors[1], +}, { + .num_paths = 1, + .vectors = &dpu_ebi_bus_vectors[2], +} }; +static struct msm_bus_scale_pdata dpu_ebi_bus_scale_table = { + .usecase = dpu_ebi_bus_usecases, + .num_usecases = ARRAY_SIZE(dpu_ebi_bus_usecases), + .name = "mdss_ebi", +}; +#endif + static const char *data_bus_name[DPU_POWER_HANDLE_DBUS_ID_MAX] = { [DPU_POWER_HANDLE_DBUS_ID_MNOC] = "qcom,dpu-data-bus", [DPU_POWER_HANDLE_DBUS_ID_LLCC] = "qcom,dpu-llcc-bus", @@ -276,93 +398,54 @@ static void dpu_power_data_bus_unregister( } } -static int dpu_power_data_bus_parse(struct platform_device *pdev, - struct dpu_power_data_bus_handle *pdbus, const char *name) +static int dpu_power_data_bus_register(struct dpu_power_handle *phandle, + int index) { - struct device_node *node; - int rc = 0; - int paths; - - pdbus->bus_channels = 1; - rc = of_property_read_u32(pdev->dev.of_node, - "qcom,dpu-dram-channels", &pdbus->bus_channels); - if (rc) { - pr_debug("number of channels property not specified\n"); - rc = 0; - } + struct dpu_power_data_bus_handle *pdbus = &phandle->data_bus_handle[index]; + pdbus->bus_channels = 2; pdbus->nrt_axi_port_cnt = 0; - rc = of_property_read_u32(pdev->dev.of_node, - "qcom,dpu-num-nrt-paths", - &pdbus->nrt_axi_port_cnt); - if (rc) { - pr_debug("number of axi port property not specified\n"); - rc = 0; + pdbus->axi_port_cnt = 1; + + switch (index) { + case DPU_POWER_HANDLE_DBUS_ID_MNOC: + pdbus->data_bus_scale_table = &dpu_data_bus_scale_table; + pdbus->axi_port_cnt = 2; + break; + case DPU_POWER_HANDLE_DBUS_ID_LLCC: + pdbus->data_bus_scale_table = &dpu_llcc_bus_scale_table; + break; + case DPU_POWER_HANDLE_DBUS_ID_EBI: + pdbus->data_bus_scale_table = &dpu_ebi_bus_scale_table; + break; + default: + pr_err("invalid data_bus type: %d", index); + return -EINVAL; } - node = of_get_child_by_name(pdev->dev.of_node, name); - if (node) { - rc = of_property_read_u32(node, - "qcom,msm-bus,num-paths", &paths); - if (rc) { - pr_err("Error. qcom,msm-bus,num-paths not found\n"); - return rc; - } - pdbus->axi_port_cnt = paths; - - pdbus->data_bus_scale_table = - msm_bus_pdata_from_node(pdev, node); - if (IS_ERR_OR_NULL(pdbus->data_bus_scale_table)) { - pr_err("reg bus handle parsing failed\n"); - rc = PTR_ERR(pdbus->data_bus_scale_table); - if (!pdbus->data_bus_scale_table) - rc = -EINVAL; - goto end; - } - pdbus->data_bus_hdl = msm_bus_scale_register_client( - pdbus->data_bus_scale_table); - if (!pdbus->data_bus_hdl) { - pr_err("data_bus_client register failed\n"); - rc = -EINVAL; - goto end; - } - pr_debug("register %s data_bus_hdl=%x\n", name, - pdbus->data_bus_hdl); + pdbus->data_bus_hdl = msm_bus_scale_register_client( + pdbus->data_bus_scale_table); + if (!pdbus->data_bus_hdl) { + pr_err("data_bus_client register failed\n"); + return -EINVAL; } + pr_debug("register %s data_bus_hdl=%x\n", data_bus_name[index], + pdbus->data_bus_hdl); -end: - return rc; + return 0; } -static int dpu_power_reg_bus_parse(struct platform_device *pdev, - struct dpu_power_handle *phandle) +static int dpu_power_reg_bus_register(struct dpu_power_handle *phandle) { - struct device_node *node; - struct msm_bus_scale_pdata *bus_scale_table; - int rc = 0; - - node = of_get_child_by_name(pdev->dev.of_node, "qcom,dpu-reg-bus"); - if (node) { - bus_scale_table = msm_bus_pdata_from_node(pdev, node); - if (IS_ERR_OR_NULL(bus_scale_table)) { - pr_err("reg bus handle parsing failed\n"); - rc = PTR_ERR(bus_scale_table); - if (!bus_scale_table) - rc = -EINVAL; - goto end; - } - phandle->reg_bus_hdl = msm_bus_scale_register_client( - bus_scale_table); - if (!phandle->reg_bus_hdl) { - pr_err("reg_bus_client register failed\n"); - rc = -EINVAL; - goto end; - } - pr_debug("register reg_bus_hdl=%x\n", phandle->reg_bus_hdl); + phandle->reg_bus_hdl = msm_bus_scale_register_client( + &dpu_reg_bus_scale_table); + if (!phandle->reg_bus_hdl) { + pr_err("reg_bus_client register failed\n"); + return -EINVAL; } + pr_debug("register reg_bus_hdl=%x\n", phandle->reg_bus_hdl); -end: - return rc; + return 0; } static void dpu_power_reg_bus_unregister(u32 reg_bus_hdl) @@ -419,8 +502,8 @@ static int dpu_power_reg_bus_update(u32 reg_bus_hdl, u32 usecase_ndx) return rc; } #else -static int dpu_power_data_bus_parse(struct platform_device *pdev, - struct dpu_power_data_bus_handle *pdbus, const char *name) +static int dpu_power_data_bus_register(struct dpu_power_handle *phandle, + int index) { return 0; } @@ -438,8 +521,7 @@ int dpu_power_data_bus_set_quota(struct dpu_power_handle *phandle, return 0; } -static int dpu_power_reg_bus_parse(struct platform_device *pdev, - struct dpu_power_handle *phandle) +static int dpu_power_reg_bus_register(struct dpu_power_handle *phandle) { return 0; } @@ -473,7 +555,7 @@ int dpu_power_resource_init(struct platform_device *pdev, phandle->dev = &pdev->dev; - rc = dpu_power_reg_bus_parse(pdev, phandle); + rc = dpu_power_reg_bus_register(phandle); if (rc) { pr_err("register bus parse failed rc=%d\n", rc); return rc; @@ -481,9 +563,7 @@ int dpu_power_resource_init(struct platform_device *pdev, for (i = DPU_POWER_HANDLE_DBUS_ID_MNOC; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) { - rc = dpu_power_data_bus_parse(pdev, - &phandle->data_bus_handle[i], - data_bus_name[i]); + rc = dpu_power_data_bus_register(phandle, i); if (rc) { pr_err("register data bus parse failed id=%d rc=%d\n", i, rc);