diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt
index 90cd3e0..a4407b8 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu.txt
+++ b/Documentation/devicetree/bindings/display/msm/dpu.txt
@@ -1,206 +1,124 @@
 Qualcomm Technologies, Inc. DPU KMS
 
-Snapdragon Display Engine implements Linux DRM/KMS APIs to drive user
-interface to different panel interfaces. DPU driver is the core of
-display subsystem which manage all data paths to different panel interfaces.
-
-Required properties
-- compatible: Must be "qcom,dpu-kms"
-- compatible: "msm-hdmi-audio-codec-rx";
-- reg: Offset and length of the register set for the device.
-- reg-names : Names to refer to register sets related to this device
-- clocks: List of Phandles for clock device nodes
-    needed by the device.
-- clock-names: List of clock names needed by the device.
-- mmagic-supply: Phandle for mmagic mdss supply regulator device node.
-- vdd-supply: Phandle for vdd regulator device node.
-- interrupt-parent: Must be core interrupt controller.
-- interrupts: Interrupt associated with MDSS.
-- interrupt-controller: Mark the device node as an interrupt controller.
-- #interrupt-cells: Should be one. The first cell is interrupt number.
-- iommus: Specifies the SID's used by this context bank.
+Description:
+
+Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
+sub-blocks like DPU display controller, DSI and DP interfaces etc.
+The DPU display controller is found in SDM845 SoC.
+
+MDSS:
+Required properties:
+- compatible: "qcom,dpu-mdss"
+- reg: physical base address and length of contoller's registers.
+- reg-names: register region names. The following region is required:
+  * "mdss_phys"
+- power-domains: a power domain consumer specifier according to
+  Documentation/devicetree/bindings/power/power_domain.txt
+- clocks: list of phandles for clock device nodes needed by the device.
+- clock-names: device clock names, must be in same order as clocks property.
+  The following clocks are required:
+  * "iface"
+  * "bus"
+  * "core"
+- interrupts: interrupt signal from MDSS.
+- interrupt-controller: identifies the node as an interrupt controller.
+- #interrupt-cells: specifies the number of cells needed to encode an interrupt
+  source, should be 1.
+- iommus: phandle of iommu device node.
+- #address-cells: number of address cells for the MDSS children. Should be 1.
+- #size-cells: Should be 1.
+- ranges: parent bus address space is the same as the child bus address space.
 
 Optional properties:
-- clock-rate:		List of clock rates in Hz.
-- clock-max-rate:	List of maximum clock rate in Hz that this device supports.
-- qcom,platform-supply-entries:	A node that lists the elements of the supply. There
-				can be more than one instance of this binding,
-				in which case the entry would be appended with
-				the supply entry index.
-				e.g. qcom,platform-supply-entry@0
-				-- reg: offset and length of the register set for the device.
-				-- qcom,supply-name: name of the supply (vdd/vdda/vddio)
-				-- qcom,supply-min-voltage: minimum voltage level (uV)
-				-- qcom,supply-max-voltage: maximum voltage level (uV)
-				-- qcom,supply-enable-load: load drawn (uA) from enabled supply
-				-- qcom,supply-disable-load: load drawn (uA) from disabled supply
-				-- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on
-				-- qcom,supply-post-on-sleep: time to sleep (ms) after turning on
-				-- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off
-				-- qcom,supply-post-off-sleep: time to sleep (ms) after turning off
-- qcom,dpu-dram-channels:	This represents the number of channels in the
-				Bus memory controller.
-- qcom,dpu-num-nrt-paths:	Integer property represents the number of non-realtime
-				paths in each Bus Scaling Usecase. This value depends on
-				number of AXI ports that are dedicated to non-realtime VBIF
-				for particular chipset.
-				These paths must be defined after rt-paths in
-				"qcom,msm-bus,vectors-KBps" vector request.
-
-Bus Scaling Subnodes:
-- qcom,dpu-reg-bus:		Property to provide Bus scaling for register access for
-				mdss blocks.
-- qcom,dpu-data-bus:		Property to provide Bus scaling for data bus access for
-				mdss blocks.
-- qcom,dpu-llcc-bus:		Property to provide Bus scaling for data bus access for
-				mnoc to llcc.
-- qcom,dpu-ebi-bus:		Property to provide Bus scaling for data bus access for
-				llcc to ebi.
-
-- qcom,dpu-inline-rotator:	A 2 cell property, with format of (rotator phandle,
-				instance id), of inline rotator device.
-
-Bus Scaling Data:
-- qcom,msm-bus,name:		String property describing client name.
-- qcom,msm-bus,num-cases:	This is the number of Bus Scaling use cases
-				defined in the vectors property.
-- qcom,msm-bus,num-paths:	This represents the number of paths in each
-				Bus Scaling Usecase.
-- qcom,msm-bus,vectors-KBps:	* A series of 4 cell properties, with a format
-				of (src, dst, ab, ib) which is defined at
-				Documentation/devicetree/bindings/arm/msm/msm_bus.txt
-				* Current values of src & dst are defined at
-				include/linux/msm-bus-board.h
-
-SMMU Subnodes:
-- smmu_dpu_****:		Child nodes representing dpu smmu virtual
-				devices
-
-Subnode properties:
-- compatible:			Compatible names used for smmu devices.
-				names should be:
-				"qcom,smmu_dpu_unsec": smmu context bank device
-				for unsecure dpu real time domain.
-				"qcom,smmu_dpu_sec": smmu context bank device
-				for secure dpu real time domain.
-				"qcom,smmu_dpu_nrt_unsec": smmu context bank device
-				for unsecure dpu non-real time domain.
-				"qcom,smmu_dpu_nrt_sec": smmu context bank device
-				for secure dpu non-real time domain.
-
-
-Please refer to ../../interrupt-controller/interrupts.txt for a general
-description of interrupt bindings.
+- clock-frequency: list of clock frequencies sorted in the same order as the
+  clocks property.
+
+MDP:
+Required properties:
+- compatible: "qcom,dpu"
+- reg: physical base address and length of controller's registers.
+- reg-names : register region names. The following region is required:
+  * "mdp_phys"
+- clocks: list of phandles for clock device nodes needed by the device.
+- clock-names: device clock names, must be in same order as clocks property.
+  The following clocks are required.
+  * "bus"
+  * "iface"
+  * "core"
+  * "vsync"
+- interrupt-parent: phandle to MDSS block.
+- interrupts: interrupt line from DPU to MDSS.
+- ports: contains the list of output ports from DPU device. These ports connect
+  to interfaces that are external to the DPU hardware, such as DSI, DP etc.
+
+  Each output port contains an endpoint that describes how it is connected to an
+  external interface. These are described by the standard properties documented
+  here:
+	Documentation/devicetree/bindings/graph.txt
+	Documentation/devicetree/bindings/media/video-interfaces.txt
+
+	Port 0 -> DPU_INTF1 (DSI1)
+	Port 1 -> DPU_INTF2 (DSI2)
+
+Optional properties:
+- clock-frequency: list of clock frequencies sorted in the same order as the
+  clocks property.
 
 Example:
-  mdss_mdp: qcom,mdss_mdp@900000 {
-    compatible = "qcom,dpu-kms";
-    reg = <0x00900000 0x90000>,
-          <0x009b0000 0x1040>,
-          <0x009b8000 0x1040>,
-          <0x0aeac000 0x00f0>;
-    reg-names = "mdp_phys",
-      "vbif_phys",
-      "vbif_nrt_phys",
-      "regdma_phys";
-    clocks = <&clock_mmss clk_mdss_ahb_clk>,
-      <&clock_mmss clk_mdss_axi_clk>,
-      <&clock_mmss clk_mdp_clk_src>,
-      <&clock_mmss clk_mdss_mdp_vote_clk>,
-      <&clock_mmss clk_smmu_mdp_axi_clk>,
-      <&clock_mmss clk_mmagic_mdss_axi_clk>,
-      <&clock_mmss clk_mdss_vsync_clk>;
-    clock-names = "iface_clk",
-      "bus_clk",
-      "core_clk_src",
-      "core_clk",
-      "iommu_clk",
-      "mmagic_clk",
-      "vsync_clk";
-    clock-rate = <0>, <0>, <0>;
-    clock-max-rate= <0 320000000 0>;
-    mmagic-supply = <&gdsc_mmagic_mdss>;
-    vdd-supply = <&gdsc_mdss>;
-    interrupt-parent = <&intc>;
-    interrupts = <0 83 0>;
-    interrupt-controller;
-    #interrupt-cells = <1>;
-    iommus = <&mdp_smmu 0>;
-
-    qcom,dpu-dram-channels = <2>;
-    qcom,dpu-num-nrt-paths = <1>;
-
-    qcom,msm-hdmi-audio-rx {
-        compatible = "qcom,msm-hdmi-audio-codec-rx";
-    };
-
-    qcom,platform-supply-entries {
-       #address-cells = <1>;
-       #size-cells = <0>;
-       qcom,platform-supply-entry@0 {
-           reg = <0>;
-           qcom,supply-name = "vdd";
-           qcom,supply-min-voltage = <0>;
-           qcom,supply-max-voltage = <0>;
-           qcom,supply-enable-load = <0>;
-           qcom,supply-disable-load = <0>;
-           qcom,supply-pre-on-sleep = <0>;
-           qcom,supply-post-on-sleep = <0>;
-           qcom,supply-pre-off-sleep = <0>;
-           qcom,supply-post-off-sleep = <0>;
-        };
-    };
-
-    qcom,dpu-data-bus {
-        qcom,msm-bus,name = "mdss_dpu";
-        qcom,msm-bus,num-cases = <3>;
-        qcom,msm-bus,num-paths = <3>;
-        qcom,msm-bus,vectors-KBps =
-            <22 512 0 0>, <23 512 0 0>, <25 512 0 0>,
-            <22 512 0 6400000>, <23 512 0 6400000>,
-                <25 512 0 6400000>,
-            <22 512 0 6400000>, <23 512 0 6400000>,
-                <25 512 0 6400000>;
-    };
-    qcom,dpu-llcc-bus {
-        qcom,msm-bus,name = "mdss_dpu_llcc";
-        qcom,msm-bus,num-cases = <3>;
-        qcom,msm-bus,num-paths = <1>;
-        qcom,msm-bus,vectors-KBps =
-            <132 770 0 0>,
-            <132 770 0 6400000>,
-            <132 770 0 6400000>;
-    };
-    qcom,dpu-ebi-bus {
-        qcom,msm-bus,name = "mdss_dpu_ebi";
-        qcom,msm-bus,num-cases = <3>;
-        qcom,msm-bus,num-paths = <1>;
-        qcom,msm-bus,vectors-KBps =
-            <129 512 0 0>,
-            <129 512 0 6400000>,
-            <129 512 0 6400000>;
-    };
-
-    qcom,dpu-reg-bus {
-        /* Reg Bus Scale Settings */
-        qcom,msm-bus,name = "mdss_reg";
-        qcom,msm-bus,num-cases = <4>;
-        qcom,msm-bus,num-paths = <1>;
-        qcom,msm-bus,active-only;
-        qcom,msm-bus,vectors-KBps =
-              <1 590 0 0>,
-              <1 590 0 76800>,
-              <1 590 0 160000>,
-              <1 590 0 320000>;
-        };
-
-    smmu_kms_unsec: qcom,smmu_kms_unsec_cb {
-        compatible = "qcom,smmu_dpu_unsec";
-        iommus = <&mmss_smmu 0>;
-    };
-
-    smmu_kms_sec: qcom,smmu_kms_sec_cb {
-        compatible = "qcom,smmu_dpu_sec";
-        iommus = <&mmss_smmu 1>;
-    };
-  };
+
+	mdss: mdss@ae00000 {
+		compatible = "qcom,dpu-mdss";
+		reg = <0xae00000 0x1000>;
+		reg-names = "mdss_phys";
+
+		power-domains = <&clock_dispcc 0>;
+
+		clocks = <&gcc GCC_DISP_AHB_CLK>,
+				 <&gcc GCC_DISP_AXI_CLK>,
+				 <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
+		clock-names = "gcc_iface", "gcc_bus", "core_clk";
+
+		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+
+		iommus = <&apps_smmu 0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		mdss_mdp: mdp@ae01000 {
+			compatible = "qcom,dpu";
+			reg = <0x0ae01000 0x8f000>;
+			reg-names = "mdp_phys";
+
+			clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
+					 <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
+					 <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
+			clock-names = "iface_clk", "bus_clk", "core_clk", "vsync_clk";
+
+			interrupt-parent = <&mdss>;
+			interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					dpu_intf1_out: endpoint {
+						remote-endpoint = <&dsi0_in>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					dpu_intf2_out: endpoint {
+						remote-endpoint = <&dsi1_in>;
+					};
+				};
+			};
+		};
+	};
