From patchwork Wed Jun 6 11:41:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Nischal X-Patchwork-Id: 10450117 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 122B560234 for ; Wed, 6 Jun 2018 11:43:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 02EE729A5C for ; Wed, 6 Jun 2018 11:43:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EB25029A6D; Wed, 6 Jun 2018 11:43:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7ABBC29A5C for ; Wed, 6 Jun 2018 11:43:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752230AbeFFLm0 (ORCPT ); Wed, 6 Jun 2018 07:42:26 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:43288 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752224AbeFFLmX (ORCPT ); Wed, 6 Jun 2018 07:42:23 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 13B02607E5; Wed, 6 Jun 2018 11:42:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1528285343; bh=0lcnGbqU+Z2LCYE3hVo1+e3TXvgVRL/p5y4aXh+SzUc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eUIXmjhYnV0y74vTwIeOzH96S/qAUzFLspwZkti/OxkTf5TqT95bBZi0aoU1lYOqq t8Oduf8Kk2d1vKgwTYVBusK0d0FjgFCc98S1R+4Wm/RhCwEL2dAeKmP3JElh5VhIpO bg0nUHvfwG+U2gwu1K9GUjdFTpoi5MC1J4veIUEs= Received: from anischal-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: anischal@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 1648B60767; Wed, 6 Jun 2018 11:42:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1528285342; bh=0lcnGbqU+Z2LCYE3hVo1+e3TXvgVRL/p5y4aXh+SzUc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jSAen/LihLWl8kWUApBi8Zp3AmYQ3UffZTus9O4+W2kwU6zpkpoLGgvnOOVuBKpdN LBZMXDP34p7AObesh+4pik12vgfu08RQ65N3/u3P8ktAuY4vbZuLNWHErkEAoVxIpO 4nxS2Es+60rLsOxZfC/lVMOkMwy6FrwjyZSNY7NE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 1648B60767 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=anischal@codeaurora.org From: Amit Nischal To: Stephen Boyd , Michael Turquette Cc: Andy Gross , David Brown , Rajendra Nayak , Odelu Kukatla , Taniya Das , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Amit Nischal Subject: [PATCH 2/4] clk: qcom: Add clk_rcg2_gfx3d_ops for SDM845 Date: Wed, 6 Jun 2018 17:11:46 +0530 Message-Id: <1528285308-25477-3-git-send-email-anischal@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1528285308-25477-1-git-send-email-anischal@codeaurora.org> References: <1528285308-25477-1-git-send-email-anischal@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP To turn on the gpu_gx_gdsc, there is a hardware requirement to turn on the root clock (GFX3D RCG) first which would be the turn on signal for the gdsc along with the SW_COLLAPSE. As per the current implementation of clk_rcg2_shared_ops, it clears the root_enable bit in the enable() and set_rate() clock ops. But due to the above said requirement for GFX3D shared RCG, root_enable bit would be already set by gdsc driver and rcg2_shared_ops should not clear the root unless the disable is called. Add support for the same by reusing the existing clk_rcg2_shared_ops and deriving "clk_rcg2_gfx3d_ops" clk_ops for GFX3D clock to take care of the root set/clear requirement. Signed-off-by: Amit Nischal --- drivers/clk/qcom/clk-rcg.h | 1 + drivers/clk/qcom/clk-rcg2.c | 78 +++++++++++++++++++++++++++++++++------------ 2 files changed, 58 insertions(+), 21 deletions(-) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index b209a2f..c8c9558 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -160,5 +160,6 @@ struct clk_rcg2 { extern const struct clk_ops clk_pixel_ops; extern const struct clk_ops clk_gfx3d_ops; extern const struct clk_ops clk_rcg2_shared_ops; +extern const struct clk_ops clk_rcg2_gfx3d_ops; #endif diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 52208d4..491e710 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -823,28 +823,12 @@ static int clk_rcg2_clear_force_enable(struct clk_hw *hw) CMD_ROOT_EN, 0); } -static int -clk_rcg2_shared_force_enable_clear(struct clk_hw *hw, const struct freq_tbl *f) -{ - struct clk_rcg2 *rcg = to_clk_rcg2(hw); - int ret; - - ret = clk_rcg2_set_force_enable(hw); - if (ret) - return ret; - - ret = clk_rcg2_configure(rcg, f); - if (ret) - return ret; - - return clk_rcg2_clear_force_enable(hw); -} - -static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate, +static int __clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); const struct freq_tbl *f; + int ret; f = qcom_find_freq(rcg->freq_tbl, rate); if (!f) @@ -857,7 +841,23 @@ static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate, if (!__clk_is_enabled(hw->clk)) return __clk_rcg2_configure(rcg, f); - return clk_rcg2_shared_force_enable_clear(hw, f); + ret = clk_rcg2_set_force_enable(hw); + if (ret) + return ret; + + return clk_rcg2_configure(rcg, f); +} + +static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + int ret; + + ret = __clk_rcg2_shared_set_rate(hw, rate, parent_rate); + if (ret) + return ret; + + return clk_rcg2_clear_force_enable(hw); } static int clk_rcg2_shared_set_rate_and_parent(struct clk_hw *hw, @@ -866,7 +866,7 @@ static int clk_rcg2_shared_set_rate_and_parent(struct clk_hw *hw, return clk_rcg2_shared_set_rate(hw, rate, parent_rate); } -static int clk_rcg2_shared_enable(struct clk_hw *hw) +static int __clk_rcg2_shared_enable(struct clk_hw *hw) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); int ret; @@ -879,7 +879,14 @@ static int clk_rcg2_shared_enable(struct clk_hw *hw) if (ret) return ret; - ret = update_config(rcg); + return update_config(rcg); +} + +static int clk_rcg2_shared_enable(struct clk_hw *hw) +{ + int ret; + + ret = __clk_rcg2_shared_enable(hw); if (ret) return ret; @@ -929,3 +936,32 @@ static void clk_rcg2_shared_disable(struct clk_hw *hw) .set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent, }; EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops); + +static int clk_rcg2_gfx3d_enable(struct clk_hw *hw) +{ + return __clk_rcg2_shared_enable(hw); +} + +static int clk_rcg2_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + return __clk_rcg2_shared_set_rate(hw, rate, parent_rate); +} + +static int clk_rcg2_gfx3d_set_rate_and_parent(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate, u8 index) +{ + return clk_rcg2_gfx3d_set_rate(hw, rate, parent_rate); +} + +const struct clk_ops clk_rcg2_gfx3d_ops = { + .enable = clk_rcg2_gfx3d_enable, + .disable = clk_rcg2_shared_disable, + .get_parent = clk_rcg2_get_parent, + .set_parent = clk_rcg2_set_parent, + .recalc_rate = clk_rcg2_recalc_rate, + .determine_rate = clk_rcg2_determine_rate, + .set_rate = clk_rcg2_gfx3d_set_rate, + .set_rate_and_parent = clk_rcg2_gfx3d_set_rate_and_parent, +}; +EXPORT_SYMBOL_GPL(clk_rcg2_gfx3d_ops);