From patchwork Mon Jun 11 17:25:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Raju P.L.S.S.S.N" X-Patchwork-Id: 10458543 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 97B9860467 for ; Mon, 11 Jun 2018 17:28:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 84B7827E01 for ; Mon, 11 Jun 2018 17:28:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 788A628501; Mon, 11 Jun 2018 17:28:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, FROM_LOCAL_NOVOWEL, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E1E2127E01 for ; Mon, 11 Jun 2018 17:28:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934408AbeFKR2p (ORCPT ); Mon, 11 Jun 2018 13:28:45 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:52430 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934225AbeFKR0s (ORCPT ); Mon, 11 Jun 2018 13:26:48 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id D66666089E; Mon, 11 Jun 2018 17:26:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1528738007; bh=WWG/yT9rn0RjJZfDzxSVq99SR0HBL42v7lobgKCREnY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mq03hypIl7Amjea5KvhTYl6QytkKGcfnpikjY1Hw1eVI2eZvs8OYtn/weaNR0a5gt yQJrHP5X88mRE9SWpckuFCd5WTZ2usNXQq0yG2a5ImrCtBxrqGgLCb9hZEdYieZ5tc oBDrmOsa6KPEy8SIEaoFq6f40ZO7tKRmRm3zyB1c= Received: from rplsssn-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: rplsssn@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5B9456074D; Mon, 11 Jun 2018 17:26:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1528737996; bh=WWG/yT9rn0RjJZfDzxSVq99SR0HBL42v7lobgKCREnY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GV4+J69UH8pzUTIXwd+wsIM8vF/Yel67MgUa+ozbiYXHEkOZGVcDxIInLgLp5u2nG 2Aw3oLWHMwLUqQLtOg/18gigUPiUloeltDxlLrfVh8lBqdSZfOs8knqRwaefhD9Psc 2qEZrHlBid2pT8g5J9BDojg9TOII0Q1ngue+FPIM= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5B9456074D Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rplsssn@codeaurora.org From: Raju P L S S S N To: andy.gross@linaro.org, david.brown@linaro.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org Cc: rnayak@codeaurora.org, bjorn.andersson@linaro.org, linux-kernel@vger.kernel.org, sboyd@kernel.org, evgreen@chromium.org, dianders@chromium.org, mka@chromium.org, ilina@codeaurora.org, devicetree@vger.kernel.org Subject: [PATCH v10 02/10] dt-bindings: introduce RPMH RSC bindings for Qualcomm SoCs Date: Mon, 11 Jun 2018 22:55:41 +0530 Message-Id: <1528737949-17495-3-git-send-email-rplsssn@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1528737949-17495-1-git-send-email-rplsssn@codeaurora.org> References: <1528737949-17495-1-git-send-email-rplsssn@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Lina Iyer Add device binding documentation for Qualcomm Technology Inc's RPMH RSC driver. The driver is used for communicating resource state requests for shared resources. Cc: devicetree@vger.kernel.org Signed-off-by: Lina Iyer Reviewed-by: Rob Herring --- Changes in v8: - Describe IRQ for all DRVs Changes in v7: - Fix example Changes in v6: - Address comments from Stephen Boyd Changes in v3: - Move to soc/qcom - Amend text per Stephen's suggestions Changes in v2: - Amend text to describe the registers in reg property - Add reg-names for the registers - Update examples to use GIC_SPI in interrupts instead of 0 - Rephrase incorrect description Changes in v3: - Fix unwanted capitalization - Remove clients from the examples, this doc does not describe them - Rephrase introductory paragraph - Remove hardware specifics from DT bindings --- .../devicetree/bindings/soc/qcom/rpmh-rsc.txt | 137 +++++++++++++++++++++ 1 file changed, 137 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt diff --git a/Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt b/Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt new file mode 100644 index 0000000..e15c100 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt @@ -0,0 +1,137 @@ +RPMH RSC: +------------ + +Resource Power Manager Hardened (RPMH) is the mechanism for communicating with +the hardened resource accelerators on Qualcomm SoCs. Requests to the resources +can be written to the Trigger Command Set (TCS) registers and using a (addr, +val) pair and triggered. Messages in the TCS are then sent in sequence over an +internal bus. + +The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity +(Resource State Coordinator a.k.a RSC) that can handle multiple sleep and +active/wake resource requests. Multiple such DRVs can exist in a SoC and can +be written to from Linux. The structure of each DRV follows the same template +with a few variations that are captured by the properties here. + +A TCS may be triggered from Linux or triggered by the F/W after all the CPUs +have powered off to facilitate idle power saving. TCS could be classified as - + + SLEEP /* Triggered by F/W */ + WAKE /* Triggered by F/W */ + ACTIVE /* Triggered by Linux */ + CONTROL /* Triggered by F/W */ + +The order in which they are described in the DT, should match the hardware +configuration. + +Requests can be made for the state of a resource, when the subsystem is active +or idle. When all subsystems like Modem, GPU, CPU are idle, the resource state +will be an aggregate of the sleep votes from each of those subsystems. Clients +may request a sleep value for their shared resources in addition to the active +mode requests. + +Properties: + +- compatible: + Usage: required + Value type: + Definition: Should be "qcom,rpmh-rsc". + +- reg: + Usage: required + Value type: + Definition: The first register specifies the base address of the + DRV(s). The number of DRVs in the dependent on the RSC. + The tcs-offset specifies the start address of the + TCS in the DRVs. + +- reg-names: + Usage: required + Value type: + Definition: Maps the register specified in the reg property. Must be + "drv-0", "drv-1", "drv-2" etc and "tcs-offset". The + +- interrupts: + Usage: required + Value type: + Definition: The interrupt that trips when a message complete/response + is received for this DRV from the accelerators. + +- qcom,drv-id: + Usage: required + Value type: + Definition: The id of the DRV in the RSC block that will be used by + this controller. + +- qcom,tcs-config: + Usage: required + Value type: + Definition: The tuple defining the configuration of TCS. + Must have 2 cells which describe each TCS type. + . + The order of the TCS must match the hardware + configuration. + - Cell #1 (TCS Type): TCS types to be specified - + SLEEP_TCS + WAKE_TCS + ACTIVE_TCS + CONTROL_TCS + - Cell #2 (Number of TCS): + +- label: + Usage: optional + Value type: + Definition: Name for the RSC. The name would be used in trace logs. + +Drivers that want to use the RSC to communicate with RPMH must specify their +bindings as child nodes of the RSC controllers they wish to communicate with. + +Example 1: + +For a TCS whose RSC base address is is 0x179C0000 and is at a DRV id of 2, the +register offsets for DRV2 start at 0D00, the register calculations are like +this - +DRV0: 0x179C0000 +DRV2: 0x179C0000 + 0x10000 = 0x179D0000 +DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000 +TCS-OFFSET: 0xD00 + + apps_rsc: rsc@179c0000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x179c0000 0x10000>, + <0x179d0000 0x10000>, + <0x179e0000 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + }; + +Example 2: + +For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the +register offsets for DRV0 start at 01C00, the register calculations are like +this - +DRV0: 0xAF20000 +TCS-OFFSET: 0x1C00 + + disp_rsc: rsc@af20000 { + label = "disp_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0xaf20000 0x10000>; + reg-names = "drv-0"; + interrupts = ; + qcom,tcs-offset = <0x1c00>; + qcom,drv-id = <0>; + qcom,tcs-config = , + , + , + ; + };