From patchwork Fri Aug 3 12:21:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taniya Das X-Patchwork-Id: 10555069 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EFE4D14E2 for ; Fri, 3 Aug 2018 12:21:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E42332C6CF for ; Fri, 3 Aug 2018 12:21:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E26742C6DC; Fri, 3 Aug 2018 12:21:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1E0612C6DD for ; Fri, 3 Aug 2018 12:21:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729969AbeHCORp (ORCPT ); Fri, 3 Aug 2018 10:17:45 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:48350 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727819AbeHCORp (ORCPT ); Fri, 3 Aug 2018 10:17:45 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 0C6D2602B7; Fri, 3 Aug 2018 12:21:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1533298899; bh=GgD6nizs+SnCdhij2srZRUKv39lLcmG2MW8fVA5OsZk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CBf1L+w8LUvmW9ZsPnagp1C4sa3JUyY7I79pAG9l1ZcQRCOkDdON4vLN32OH2qZGB Y5RGPImQgfiYkYD4rBkCl4mF2wCi8xyRdGTSZGX8VNnwzdjIvRG9SZHRqPdv0rZQd6 G+Re/+HSJFbj/R7+GsE7ProF1PNZNG0jHTPH2ALo= Received: from tdas-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: tdas@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 8719560AD8; Fri, 3 Aug 2018 12:21:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1533298897; bh=GgD6nizs+SnCdhij2srZRUKv39lLcmG2MW8fVA5OsZk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=F8OmoMUtP02lTpUbFnUjlLwro3I7L4+wwTeeXrewcf6SjQRYM7gcr9DitMt8c/wre 5ObyxdV0Gf3PKQNrE5zxVWLJvjPdCAUDXiNvWW5ZPo6oEsBlDPfVioesfYKzvkzUsI uLGL6pDA7Fg/aHb/do0xny5ak0GyZrkKHVI/amus= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 8719560AD8 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=tdas@codeaurora.org From: Taniya Das To: Stephen Boyd , Michael Turquette Cc: Andy Gross , David Brown , Rajendra Nayak , Amit Nischal , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, robh@kernel.org, Taniya Das Subject: [PATCH v3 2/2] clk: qcom: Add lpass clock controller driver for SDM845 Date: Fri, 3 Aug 2018 17:51:14 +0530 Message-Id: <1533298874-22863-3-git-send-email-tdas@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533298874-22863-1-git-send-email-tdas@codeaurora.org> References: <1533298874-22863-1-git-send-email-tdas@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for the lpass clock controller found on SDM845 based devices. This would allow lpass peripheral loader drivers to control the clocks to bring the subsystem out of reset. LPASS clocks present on the global clock controller would be registered with the clock framework based on the device tree flag. Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 9 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-sdm845.c | 35 +++++++ drivers/clk/qcom/lpasscc-sdm845.c | 189 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 234 insertions(+) create mode 100644 drivers/clk/qcom/lpasscc-sdm845.c -- Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation. -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 2b69cf2..7bd940d 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -254,6 +254,15 @@ config SDM_VIDEOCC_845 Say Y if you want to support video devices and functionality such as video encode and decode. +config SDM_LPASSCC_845 + tristate "SDM845 LPASS Clock Controller" + depends on COMMON_CLK_QCOM + select SDM_GCC_845 + help + Support for the LPASS clock controller on SDM845 devices. + Say Y if you want to use the LPASS branch clocks of the LPASS clock + controller to reset the LPASS subsystem. + config SPMI_PMIC_CLKDIV tristate "SPMI PMIC clkdiv Support" depends on (COMMON_CLK_QCOM && SPMI) || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 599ab91..df2bd1f 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -40,5 +40,6 @@ obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o +obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c index 0f694ed..068cf53 100644 --- a/drivers/clk/qcom/gcc-sdm845.c +++ b/drivers/clk/qcom/gcc-sdm845.c @@ -3086,6 +3086,32 @@ enum { }, }; +static struct clk_branch gcc_lpass_q6_axi_clk = { + .halt_reg = 0x47000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x47000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_lpass_q6_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_lpass_sway_clk = { + .halt_reg = 0x47008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x47008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_lpass_sway_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct gdsc pcie_0_gdsc = { .gdscr = 0x6b004, .pd = { @@ -3383,6 +3409,8 @@ enum { [GPLL4] = &gpll4.clkr, [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr, [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, + [GCC_LPASS_Q6_AXI_CLK] = NULL, + [GCC_LPASS_SWAY_CLK] = NULL, }; static const struct qcom_reset_map gcc_sdm845_resets[] = { @@ -3472,6 +3500,13 @@ static int gcc_sdm845_probe(struct platform_device *pdev) regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3); regmap_update_bits(regmap, 0x71028, 0x3, 0x3); + if (of_property_read_bool(pdev->dev.of_node, "qcom,lpass-protected")) { + gcc_sdm845_clocks[GCC_LPASS_Q6_AXI_CLK] = + &gcc_lpass_q6_axi_clk.clkr; + gcc_sdm845_clocks[GCC_LPASS_SWAY_CLK] = + &gcc_lpass_sway_clk.clkr; + } + return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap); } diff --git a/drivers/clk/qcom/lpasscc-sdm845.c b/drivers/clk/qcom/lpasscc-sdm845.c new file mode 100644 index 0000000..6f387f9 --- /dev/null +++ b/drivers/clk/qcom/lpasscc-sdm845.c @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-regmap.h" +#include "clk-branch.h" +#include "common.h" + +static struct clk_branch lpass_audio_wrapper_aon_clk = { + .halt_reg = 0x098, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_audio_wrapper_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lpass_q6ss_ahbm_aon_clk = { + .halt_reg = 0x12000, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x12000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_q6ss_ahbm_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lpass_q6ss_ahbs_aon_clk = { + .halt_reg = 0x1f000, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x1f000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_q6ss_ahbs_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +/* CLK_OFF would not toggle until LPASS is not out of reset */ +static struct clk_branch lpass_qdsp6ss_core_clk = { + .halt_reg = 0x20, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x20, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_qdsp6ss_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +/* CLK_OFF would not toggle until LPASS is not out of reset */ +static struct clk_branch lpass_qdsp6ss_xo_clk = { + .halt_reg = 0x38, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x38, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_qdsp6ss_xo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +/* CLK_OFF would not toggle until LPASS is not out of reset */ +static struct clk_branch lpass_qdsp6ss_sleep_clk = { + .halt_reg = 0x3c, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x3c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_qdsp6ss_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct regmap_config lpass_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .fast_io = true, +}; + +static struct clk_regmap *lpass_cc_sdm845_clocks[] = { + [LPASS_AUDIO_WRAPPER_AON_CLK] = &lpass_audio_wrapper_aon_clk.clkr, + [LPASS_Q6SS_AHBM_AON_CLK] = &lpass_q6ss_ahbm_aon_clk.clkr, + [LPASS_Q6SS_AHBS_AON_CLK] = &lpass_q6ss_ahbs_aon_clk.clkr, +}; + +static const struct qcom_cc_desc lpass_cc_sdm845_desc = { + .config = &lpass_regmap_config, + .clks = lpass_cc_sdm845_clocks, + .num_clks = ARRAY_SIZE(lpass_cc_sdm845_clocks), +}; + +static struct clk_regmap *lpass_qdsp6ss_sdm845_clocks[] = { + [LPASS_QDSP6SS_XO_CLK] = &lpass_qdsp6ss_xo_clk.clkr, + [LPASS_QDSP6SS_SLEEP_CLK] = &lpass_qdsp6ss_sleep_clk.clkr, + [LPASS_QDSP6SS_CORE_CLK] = &lpass_qdsp6ss_core_clk.clkr, +}; + +static const struct qcom_cc_desc lpass_qdsp6ss_sdm845_desc = { + .config = &lpass_regmap_config, + .clks = lpass_qdsp6ss_sdm845_clocks, + .num_clks = ARRAY_SIZE(lpass_qdsp6ss_sdm845_clocks), +}; + +static int lpass_clocks_sdm845_probe(struct platform_device *pdev, int index, + const struct qcom_cc_desc *desc) +{ + struct regmap *regmap; + struct resource *res; + void __iomem *base; + + res = platform_get_resource(pdev, IORESOURCE_MEM, index); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return -ENOMEM; + + regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return qcom_cc_really_probe(pdev, desc, regmap); +} + +/* LPASS CC clock controller */ +static const struct of_device_id lpass_cc_sdm845_match_table[] = { + { .compatible = "qcom,sdm845-lpasscc" }, + { } +}; +MODULE_DEVICE_TABLE(of, lpass_cc_sdm845_match_table); + +static int lpass_cc_sdm845_probe(struct platform_device *pdev) +{ + const struct qcom_cc_desc *desc; + int ret; + + lpass_regmap_config.name = "lpass_cc"; + desc = &lpass_cc_sdm845_desc; + + ret = lpass_clocks_sdm845_probe(pdev, 0, desc); + if (ret) + return ret; + + lpass_regmap_config.name = "lpass_qdsp6ss"; + desc = &lpass_qdsp6ss_sdm845_desc; + + return lpass_clocks_sdm845_probe(pdev, 1, desc); +} + +static struct platform_driver lpass_cc_sdm845_driver = { + .probe = lpass_cc_sdm845_probe, + .driver = { + .name = "sdm845-lpasscc", + .of_match_table = lpass_cc_sdm845_match_table, + }, +}; + +static int __init lpass_cc_sdm845_init(void) +{ + return platform_driver_register(&lpass_cc_sdm845_driver); +} +subsys_initcall(lpass_cc_sdm845_init); + +MODULE_LICENSE("GPL v2");