soc: qcom: Add irq clear handling during SE init

Commit Message

Alok Chauhan Oct. 3, 2018, 12:23 p.m. UTC

when the kernel inits a SE, its quite possible we have pending interrupts
from bootloaders which did not handle/clear them. So do this in kernel at
the SE init, to avoid some of it causing bad behavior, while at it also
club all the register writes needed to clear the se irqs into a function
to avoid repeating it over.

Signed-off-by: Alok Chauhan <[e-mail]>
---
 drivers/soc/qcom/qcom-geni-se.c | 25 +++++++++++++------------
 1 file changed, 13 insertions(+), 12 deletions(-)

Comments

Doug Anderson Oct. 3, 2018, 5:45 p.m. UTC | #1

Hi,

On Wed, Oct 3, 2018 at 5:24 AM Alok Chauhan <[e-mail]> wrote:
>
> when the kernel inits a SE, its quite possible we have pending interrupts
> from bootloaders which did not handle/clear them. So do this in kernel at
> the SE init, to avoid some of it causing bad behavior, while at it also
> club all the register writes needed to clear the se irqs into a function
> to avoid repeating it over.
>
> Signed-off-by: Alok Chauhan <[e-mail]>
> ---
>  drivers/soc/qcom/qcom-geni-se.c | 25 +++++++++++++------------
>  1 file changed, 13 insertions(+), 12 deletions(-)

This looks fine to me.  To clarify this doesn't fix any known issues
and it just fixes the theoretical case where somehow a IRQ was sitting
around (maybe left by the firmware) so we want to make really certain
that we start with a clean state at init time.

Reviewed-by: Douglas Anderson <[e-mail]>

Andy Gross Nov. 14, 2018, 5:51 p.m. UTC | #2

On Wed, Oct 03, 2018 at 05:53:50PM +0530, Alok Chauhan wrote:
> when the kernel inits a SE, its quite possible we have pending interrupts
> from bootloaders which did not handle/clear them. So do this in kernel at
> the SE init, to avoid some of it causing bad behavior, while at it also
> club all the register writes needed to clear the se irqs into a function
> to avoid repeating it over.
> 
> Signed-off-by: Alok Chauhan <[e-mail]>
> ---

Thanks for sending this in.  I'll apply to my queue.

Andy

Patch

diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c
index feed3db2..1422fc5 100644
--- a/drivers/soc/qcom/qcom-geni-se.c
+++ b/drivers/soc/qcom/qcom-geni-se.c
@@ -215,6 +215,16 @@  static void geni_se_io_init(void __iomem *base)
 	writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG);
 }
 
+static void geni_se_irq_clear(struct geni_se *se)
+{
+	writel_relaxed(0, se->base + SE_GSI_EVENT_EN);
+	writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR);
+	writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR);
+	writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR);
+	writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR);
+	writel_relaxed(0xffffffff, se->base + SE_IRQ_EN);
+}
+
 /**
  * geni_se_init() - Initialize the GENI serial engine
  * @se:		Pointer to the concerned serial engine.
@@ -228,6 +238,7 @@  void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr)
 {
 	u32 val;
 
+	geni_se_irq_clear(se);
 	geni_se_io_init(se->base);
 	geni_se_io_set_mode(se->base);
 
@@ -249,12 +260,7 @@  static void geni_se_select_fifo_mode(struct geni_se *se)
 	u32 proto = geni_se_read_proto(se);
 	u32 val;
 
-	writel_relaxed(0, se->base + SE_GSI_EVENT_EN);
-	writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR);
-	writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR);
-	writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR);
-	writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR);
-	writel_relaxed(0xffffffff, se->base + SE_IRQ_EN);
+	geni_se_irq_clear(se);
 
 	val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
 	if (proto != GENI_SE_UART) {
@@ -277,12 +283,7 @@  static void geni_se_select_dma_mode(struct geni_se *se)
 {
 	u32 val;
 
-	writel_relaxed(0, se->base + SE_GSI_EVENT_EN);
-	writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR);
-	writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR);
-	writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR);
-	writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR);
-	writel_relaxed(0xffffffff, se->base + SE_IRQ_EN);
+	geni_se_irq_clear(se);
 
 	val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
 	val |= GENI_DMA_MODE_EN;