From patchwork Wed Oct 3 13:44:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alok Chauhan X-Patchwork-Id: 10624843 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7E06815A7 for ; Wed, 3 Oct 2018 13:45:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6D59D287B3 for ; Wed, 3 Oct 2018 13:45:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6183D28A55; Wed, 3 Oct 2018 13:45:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D1548287B3 for ; Wed, 3 Oct 2018 13:45:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727222AbeJCUdg (ORCPT ); Wed, 3 Oct 2018 16:33:36 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:57340 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726694AbeJCUdg (ORCPT ); Wed, 3 Oct 2018 16:33:36 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 84BB560C7B; Wed, 3 Oct 2018 13:45:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1538574306; bh=kzWuYFfTiyoeClrY0eK/QW8Y7mt86vDlMXD2H3en6qg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ik53fxLaOeiADXJU+k45FrqiSP4aRJKWdu6cXGCI74BtxFRM/5Rj3m0hlVayMOyeE ukWwlqBVnVSvXZX2VNMKSmfA2ja+4ZnJtlluECjB32Q+p6h6ITQVgR1vIqftwo66kM L/0LBx1n2MtUQ0TyPhxhwTyj+amU/057wzkSuDB0= Received: from alokc-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alokc@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5052760C80; Wed, 3 Oct 2018 13:44:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1538574304; bh=kzWuYFfTiyoeClrY0eK/QW8Y7mt86vDlMXD2H3en6qg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jPJD71MXowLF3ySBrXr5vKhMPDUJiluGKInheTa1K4eQ833cIl4BgI9JM4GFbxkUK DoL6WU/++JL3QyVGn2LpifriqKRE0lsrwRyMRvFowjZdOHpuXP3HjSpKjd3RzkAmXV MBx5jAldXEubQPF/6sUEpwQeJkQXfW93oo5Q1JZM= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5052760C80 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alokc@codeaurora.org From: Alok Chauhan To: swboyd@chromium.org, dianders@chromium.org, broonie@kernel.org, mka@chromium.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, Andy Gross , David Brown , Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, devicetree@vger.kernel.org Cc: Dilip Kota , Alok Chauhan Subject: [PATCH V5 2/3] dt-bindings: soc: qcom: GENI SE SPI controller device tree binding Date: Wed, 3 Oct 2018 19:14:24 +0530 Message-Id: <1538574265-30235-3-git-send-email-alokc@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1538574265-30235-1-git-send-email-alokc@codeaurora.org> References: <1538574265-30235-1-git-send-email-alokc@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dilip Kota Move GENI SE SPI controller device-tree bindings from devicetree/bindings/soc/qcom/qcom,geni-se.txt to devicetree/bindings/spi/qcom,spi-geni-qcom.txt. Signed-off-by: Dilip Kota Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Rob Herring Signed-off-by: Alok Chauhan --- .../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 27 ++------------- .../devicetree/bindings/spi/qcom,spi-geni-qcom.txt | 39 ++++++++++++++++++++++ 2 files changed, 41 insertions(+), 25 deletions(-) create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt index b9d0c21..dab7ca9 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt @@ -53,19 +53,8 @@ Required properties: - clocks: Serial engine core clock needed by the device. Qualcomm Technologies Inc. GENI Serial Engine based SPI Controller - -Required properties: -- compatible: Must contain "qcom,geni-spi". -- reg: Must contain SPI register location and length. -- interrupts: Must contain SPI controller interrupts. -- clock-names: Must contain "se". -- clocks: Serial engine core clock needed by the device. -- #address-cells: Must be <1> to define a chip select address on - the SPI bus. -- #size-cells: Must be <0>. - -SPI slave nodes must be children of the SPI master node and conform to SPI bus -binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt. +node binding is described in +Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt. Example: geniqup@8c0000 { @@ -102,16 +91,4 @@ Example: pinctrl-1 = <&qup_1_uart_3_sleep>; }; - spi0: spi@a84000 { - compatible = "qcom,geni-spi"; - reg = <0xa84000 0x4000>; - interrupts = ; - clock-names = "se"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qup_1_spi_2_active>; - pinctrl-1 = <&qup_1_spi_2_sleep>; - #address-cells = <1>; - #size-cells = <0>; - }; } diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt new file mode 100644 index 0000000..790311a --- /dev/null +++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt @@ -0,0 +1,39 @@ +GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) + +The QUP v3 core is a GENI based AHB slave that provides a common data path +(an output FIFO and an input FIFO) for serial peripheral interface (SPI) +mini-core. + +SPI in master mode supports up to 50MHz, up to four chip selects, programmable +data path from 4 bits to 32 bits and numerous protocol variants. + +Required properties: +- compatible: Must contain "qcom,geni-spi". +- reg: Must contain SPI register location and length. +- interrupts: Must contain SPI controller interrupts. +- clock-names: Must contain "se". +- clocks: Serial engine core clock needed by the device. +- #address-cells: Must be <1> to define a chip select address on + the SPI bus. +- #size-cells: Must be <0>. + +SPI Controller nodes must be child of GENI based Qualcomm Universal +Peripharal. Please refer GENI based QUP wrapper controller node bindings +described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt. + +SPI slave nodes must be children of the SPI master node and conform to SPI bus +binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt. + +Example: + spi0: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0xa84000 0x4000>; + interrupts = ; + clock-names = "se"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_1_spi_2_active>; + pinctrl-1 = <&qup_1_spi_2_sleep>; + #address-cells = <1>; + #size-cells = <0>; + };