diff mbox series

[12/25] drm/msm/dpu: remove mode_set_complete

Message ID 1539059262-8326-13-git-send-email-jsanka@codeaurora.org (mailing list archive)
State Not Applicable, archived
Delegated to: Andy Gross
Headers show
Series reserve RM resources in CRTC state | expand

Commit Message

Jeykumar Sankaran Oct. 9, 2018, 4:27 a.m. UTC
This flag was introduced as a fix to notify modeset complete
when hw reservations were happening in both atomic_check
and atomic_commit paths. Now that we are reserving only in
atomic_check, we can get rid of this flag.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 19 +++----------------
 1 file changed, 3 insertions(+), 16 deletions(-)

Comments

Sean Paul Oct. 10, 2018, 2:59 p.m. UTC | #1
On Mon, Oct 08, 2018 at 09:27:29PM -0700, Jeykumar Sankaran wrote:
> This flag was introduced as a fix to notify modeset complete
> when hw reservations were happening in both atomic_check
> and atomic_commit paths. Now that we are reserving only in
> atomic_check, we can get rid of this flag.
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>

Reviewed-by: Sean Paul <seanpaul@chromium.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 19 +++----------------
>  1 file changed, 3 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index dd482ca..468b8fd0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -167,7 +167,6 @@ enum dpu_enc_rc_states {
>   *				clks and resources after IDLE_TIMEOUT time.
>   * @vsync_event_work:		worker to handle vsync event for autorefresh
>   * @topology:                   topology of the display
> - * @mode_set_complete:          flag to indicate modeset completion
>   * @idle_timeout:		idle timeout duration in milliseconds
>   */
>  struct dpu_encoder_virt {
> @@ -204,7 +203,6 @@ struct dpu_encoder_virt {
>  	struct kthread_delayed_work delayed_off_work;
>  	struct kthread_work vsync_event_work;
>  	struct msm_display_topology topology;
> -	bool mode_set_complete;
>  
>  	u32 idle_timeout;
>  };
> @@ -636,18 +634,9 @@ static int dpu_encoder_virt_atomic_check(
>  
>  	topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
>  
> -	if (!ret) {
> -		/*
> -		 * Avoid reserving resources when mode set is pending. Topology
> -		 * info may not be available to complete reservation.
> -		 */
> -		if (drm_atomic_crtc_needs_modeset(crtc_state)
> -				&& dpu_enc->mode_set_complete) {
> -			ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state,
> -					     topology, false);
> -			dpu_enc->mode_set_complete = false;
> -		}
> -	}
> +	if (!ret && drm_atomic_crtc_needs_modeset(crtc_state))
> +		ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state,
> +				     topology, false);
>  
>  	if (!ret)
>  		drm_mode_set_crtcinfo(adj_mode, 0);
> @@ -1060,8 +1049,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
>  				phys->ops.mode_set(phys, mode, adj_mode);
>  		}
>  	}
> -
> -	dpu_enc->mode_set_complete = true;
>  }
>  
>  static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index dd482ca..468b8fd0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -167,7 +167,6 @@  enum dpu_enc_rc_states {
  *				clks and resources after IDLE_TIMEOUT time.
  * @vsync_event_work:		worker to handle vsync event for autorefresh
  * @topology:                   topology of the display
- * @mode_set_complete:          flag to indicate modeset completion
  * @idle_timeout:		idle timeout duration in milliseconds
  */
 struct dpu_encoder_virt {
@@ -204,7 +203,6 @@  struct dpu_encoder_virt {
 	struct kthread_delayed_work delayed_off_work;
 	struct kthread_work vsync_event_work;
 	struct msm_display_topology topology;
-	bool mode_set_complete;
 
 	u32 idle_timeout;
 };
@@ -636,18 +634,9 @@  static int dpu_encoder_virt_atomic_check(
 
 	topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
 
-	if (!ret) {
-		/*
-		 * Avoid reserving resources when mode set is pending. Topology
-		 * info may not be available to complete reservation.
-		 */
-		if (drm_atomic_crtc_needs_modeset(crtc_state)
-				&& dpu_enc->mode_set_complete) {
-			ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state,
-					     topology, false);
-			dpu_enc->mode_set_complete = false;
-		}
-	}
+	if (!ret && drm_atomic_crtc_needs_modeset(crtc_state))
+		ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state,
+				     topology, false);
 
 	if (!ret)
 		drm_mode_set_crtcinfo(adj_mode, 0);
@@ -1060,8 +1049,6 @@  static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
 				phys->ops.mode_set(phys, mode, adj_mode);
 		}
 	}
-
-	dpu_enc->mode_set_complete = true;
 }
 
 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)