From patchwork Tue Oct 9 13:05:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Govind Singh X-Patchwork-Id: 10632459 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5574813AA for ; Tue, 9 Oct 2018 13:06:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 31C2628BB4 for ; Tue, 9 Oct 2018 13:06:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 23BAD28DB0; Tue, 9 Oct 2018 13:06:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2CA7F28DAD for ; Tue, 9 Oct 2018 13:06:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726989AbeJIUXL (ORCPT ); Tue, 9 Oct 2018 16:23:11 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:60902 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726418AbeJIUXL (ORCPT ); Tue, 9 Oct 2018 16:23:11 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 47B0F60BFE; Tue, 9 Oct 2018 13:06:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1539090379; bh=+yRg16ZJattDjd2GGfDX/Cb6u3b+p6h6KXzJEu3OwPM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CIFL2SwE8ubtYEbPgXlUYq67zYgNLCGBFL71DQyUayWkQBcnCWpd+pPyC0c7iq4fn fP5cL+ucVY4ju1qFi3YmTjkElIXOxwNvU9IlW08ypkBqK60cbm83zH2sdo/W5tOo2s wB8KBwte3//Ykcr4ihzdjypROUrLcV4qxaqBFYH4= Received: from svishnoi-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: govinds@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id F0EAE60C5F; Tue, 9 Oct 2018 13:06:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1539090378; bh=+yRg16ZJattDjd2GGfDX/Cb6u3b+p6h6KXzJEu3OwPM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GV19g3haTcdtWeP5DNeyc0BjKrgBdRJHHYBKxezl/EKIV9V5lPJ33/QGVW+fLchGM G7PpU8UooQli6kLOrcp5Tq36w6cn3XFOJs/1Wh+YeX94xey9EOg9vYXXtjuKmXaNpm hJ7JZD2TOCt7XP223s7nG16whBYth2dyl8c1d5IM= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org F0EAE60C5F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=govinds@codeaurora.org From: Govind Singh To: bjorn.andersson@linaro.org, linux-remoteproc@vger.kernel.org, sricharan@codeaurora.org, sibis@codeaurora.org, linux-arm-msm@vger.kernel.org, andy.gross@linaro.org, david.brown@linaro.org, linux-soc@vger.kernel.org, devicetree@vger.kernel.org Cc: Govind Singh Subject: [PATCH 3/6] dt-bindings: clock: qcom: Introduce QCOM WCSS Q6DSP clock bindings Date: Tue, 9 Oct 2018 18:35:54 +0530 Message-Id: <1539090357-20853-4-git-send-email-govinds@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1539090357-20853-1-git-send-email-govinds@codeaurora.org> References: <1539090357-20853-1-git-send-email-govinds@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add device tree bindings for WiFi QDSP subsystem clock controls found in OCS405 soc. Signed-off-by: Govind Singh --- .../devicetree/bindings/clock/qcom,wcsscc.txt | 26 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,wcss-qcs404.h | 24 ++++++++++++++++++++ 2 files changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,wcsscc.txt create mode 100644 include/dt-bindings/clock/qcom,wcss-qcs404.h diff --git a/Documentation/devicetree/bindings/clock/qcom,wcsscc.txt b/Documentation/devicetree/bindings/clock/qcom,wcsscc.txt new file mode 100644 index 0000000..2b19ef0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,wcsscc.txt @@ -0,0 +1,26 @@ +Qualcomm WCSS Clock Controller Binding +----------------------------------------------- + +Required properties : +- compatible : shall contain "qcom,qcs404-wcsscc" +- #clock-cells : from common clock binding, shall contain 1. +- reg : shall contain base register address and size, + in the order + Index-0 maps to WCSS_Q6SSTOP clocks register region + Index-1 maps to WCSS_TCSR register region + Index-2 maps to WCSS_QDSP6SS register region + +Optional properties : +- reg-names : register names of WCSS domain + "wcss_q6sstop", "wcnss_tcsr", "wcss_qdsp6ss". + +Example: +The below node has to be defined in the cases where the WCSS peripheral loader +would bring the subsystem out of reset. + + clock_wcsscc: qcom,wcsscc@7000000 { + compatible = "qcom,qcs404-wcsscc"; + reg = <0x07500000 0x4e000>, <0x07550000 0x8012>, <0x07400000 0x104>; + reg-names = "wcss_q6sstop", "wcnss_tcsr", "wcss_qdsp6ss"; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/qcom,wcss-qcs404.h b/include/dt-bindings/clock/qcom,wcss-qcs404.h new file mode 100644 index 0000000..45dd659 --- /dev/null +++ b/include/dt-bindings/clock/qcom,wcss-qcs404.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_WCSS_QCS404_H +#define _DT_BINDINGS_CLK_WCSS_QCS404_H + +#define WCSS_AHBFABRIC_CBCR_CLK 0 +#define WCSS_AHBS_CBCR_CLK 1 +#define WCSS_TCM_CBCR_CLK 2 +#define WCSS_AHBM_CBCR_CLK 3 +#define WCSS_AXIM_CBCR_CLK 4 +#define WCSS_BCR_CBCR_CLK 5 +#define WCSS_LCC_CBCR_CLK 6 +#define WCSS_QDSP6SS_XO_CBCR_CLK 7 +#define WCSS_QDSP6SS_SLEEP_CBCR_CLK 8 +#define WCSS_QDSP6SS_GFMMUX_CLK 9 + +#define Q6SSTOP_QDSP6SS_RESET 0 +#define Q6SSTOP_QDSP6SS_CORE_RESET 1 +#define Q6SSTOP_QDSP6SS_BUS_RESET 2 +#define Q6SSTOP_BCR_RESET 3 +#endif