From patchwork Tue Nov 20 11:14:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 10690271 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2E3F31923 for ; Tue, 20 Nov 2018 11:15:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2185D295C3 for ; Tue, 20 Nov 2018 11:15:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 148CC2A7FC; Tue, 20 Nov 2018 11:15:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1B69E29A89 for ; Tue, 20 Nov 2018 11:15:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728411AbeKTVnh (ORCPT ); Tue, 20 Nov 2018 16:43:37 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:42954 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728352AbeKTVng (ORCPT ); Tue, 20 Nov 2018 16:43:36 -0500 Received: by mail-wr1-f67.google.com with SMTP id q18so1512363wrx.9 for ; Tue, 20 Nov 2018 03:14:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=xZcEPIfg4frvh5Hs0xnUDMuN5+SH2Ev3SNI6h8iKwZs=; b=Ae03QBU+GQwGkbonnlUfPhiDmDATEFd1gAYOd4U2kdIAyJm9PBnC1bHoA9+6S49AR7 Q8yVGJz378/f/s4vsSKJHKkNUFJgP/g0k5XUo1fDiQqT7berX0kJk9hBZ61Q6zA5XfJz wXyyWSodb4lKnyZDznTUVXYmIKTWwjDyK1UGI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=xZcEPIfg4frvh5Hs0xnUDMuN5+SH2Ev3SNI6h8iKwZs=; b=jnZDHIZabR6wzj1QxmnDHt9RXAPH6Fdw0jgMZSbSW2KXW7mvKrWJ6TkZtiVR6YKPcw 6SK4ie8GL/TkFfMQG2jnD+V9tS70/TblnEp7cDqJ/7q1JLrz4V2pSpivTrIyWJGiAzhJ dsSCJUbLclm28qjF2ez7YeQQ1o0Wm1oFQKSBJCh8HpB7+p9mTZtuFYl1RaGYeZV0ub3C qCxfBOZCTR/mkn3uM/ujSHjVhGN280rwcqaPwLlrq3d8MvZsvVG8rLbQATsBT6e1Qrdd E/tMA9whyCpgYmkRY3y26Mxc/HdoiH9otjkkBVMphCKdQ4Rar5+uFMMiSajU/lH9Yf6L jFxQ== X-Gm-Message-State: AA+aEWb76HHhEDxA7lWB1Sue/7GVPJjlgRQ8Y0hz2WS8iYmns7xrq7kH RcjydOukereggvcuoMMzwAu0nA== X-Google-Smtp-Source: AFSGD/XsuVJggo55LijR7qufmSMxF5Q3FGGwHYqc1iKTd0dBb513iuPT7I/mhknsz2bjIrAqDI/XIQ== X-Received: by 2002:adf:ae41:: with SMTP id u1mr1510793wrd.20.1542712498693; Tue, 20 Nov 2018 03:14:58 -0800 (PST) Received: from lpoulain-ThinkPad-T470p.home (atoulouse-654-1-394-222.w90-55.abo.wanadoo.fr. [90.55.193.222]) by smtp.gmail.com with ESMTPSA id q3sm13222795wrn.84.2018.11.20.03.14.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 20 Nov 2018 03:14:57 -0800 (PST) From: Loic Poulain To: andy.gross@linaro.org, david.brown@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Loic Poulain Subject: [PATCH] clk: qcom: msm8916: Additional clock rates for spi Date: Tue, 20 Nov 2018 12:14:56 +0100 Message-Id: <1542712496-24941-1-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add SPI friendly clock rates to the spi freq table. Today it's not possible to use SPI at lower than 960Khz. This patch adds 100/250/500/1000 khz configs to the table. Signed-off-by: Loic Poulain --- drivers/clk/qcom/gcc-msm8916.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c index ac2b0aa..7d9647c 100644 --- a/drivers/clk/qcom/gcc-msm8916.c +++ b/drivers/clk/qcom/gcc-msm8916.c @@ -544,7 +544,11 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { }; static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = { + F(100000, P_XO, 16, 2, 24), + F(250000, P_XO, 16, 5, 24), + F(500000, P_XO, 8, 5, 24), F(960000, P_XO, 10, 1, 2), + F(1000000, P_XO, 4, 5, 24), F(4800000, P_XO, 4, 0, 0), F(9600000, P_XO, 2, 0, 0), F(16000000, P_GPLL0, 10, 1, 5),