| Message ID | 1546620615-2389-1-git-send-email-jhugo@codeaurora.org (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | MSM8998 basic USB support | expand |
Quoting Jeffrey Hugo (2019-01-04 08:50:15) > The gcc_usb3_phy_pipe_clk is generated by the phy, but is also used by > the phy during init. The clock needs to be enabled during the init > sequence, but may not be fully active until after the init sequence is > complete. This causes a catch-22 if the clock status is checked during > enable. As a result, skip the checks to avoid the troubling situation. I will ask again, is anyone going to fix this in the phy driver? In theory it isn't needed if the phy driver can do things differently, but last time I checked I was told that the phy team said it had to be done this way.
Quoting Jeffrey Hugo (2019-01-04 08:50:15) > The gcc_usb3_phy_pipe_clk is generated by the phy, but is also used by > the phy during init. The clock needs to be enabled during the init > sequence, but may not be fully active until after the init sequence is > complete. This causes a catch-22 if the clock status is checked during > enable. As a result, skip the checks to avoid the troubling situation. > > Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> > --- Applied to clk-next
On 1/9/2019 11:59 AM, Stephen Boyd wrote: > Quoting Jeffrey Hugo (2019-01-04 08:50:15) >> The gcc_usb3_phy_pipe_clk is generated by the phy, but is also used by >> the phy during init. The clock needs to be enabled during the init >> sequence, but may not be fully active until after the init sequence is >> complete. This causes a catch-22 if the clock status is checked during >> enable. As a result, skip the checks to avoid the troubling situation. > > I will ask again, is anyone going to fix this in the phy driver? In > theory it isn't needed if the phy driver can do things differently, but > last time I checked I was told that the phy team said it had to be done > this way. > Interesting. I was unaware of past discussion(s) on this. Thank you for taking the change, but I'll try having a look to see if maybe I can prove your theory going forward.
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index 42de947..1a1806a 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -2496,7 +2496,7 @@ enum { static struct clk_branch gcc_usb3_phy_pipe_clk = { .halt_reg = 0x50004, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x50004, .enable_mask = BIT(0),
The gcc_usb3_phy_pipe_clk is generated by the phy, but is also used by the phy during init. The clock needs to be enabled during the init sequence, but may not be fully active until after the init sequence is complete. This causes a catch-22 if the clock status is checked during enable. As a result, skip the checks to avoid the troubling situation. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> --- drivers/clk/qcom/gcc-msm8998.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)