| Message ID | 1557252127-11145-3-git-send-email-jcrouse@codeaurora.org (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | drm/msm: Add dependencies for per-instance pagetables | expand |
On Tue, May 7, 2019 at 11:02 AM Jordan Crouse <jcrouse@codeaurora.org> wrote: > > When we move to 64 bit addressing for a5xx and a6xx targets we will start > seeing pagefaults at larger addresses so format them appropriately in the > log message for easier debugging. Yes please, this has confused me more than once. Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > --- > > drivers/gpu/drm/msm/msm_iommu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c > index 12bb54c..1926329 100644 > --- a/drivers/gpu/drm/msm/msm_iommu.c > +++ b/drivers/gpu/drm/msm/msm_iommu.c > @@ -30,7 +30,7 @@ static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, > struct msm_iommu *iommu = arg; > if (iommu->base.handler) > return iommu->base.handler(iommu->base.arg, iova, flags); > - pr_warn_ratelimited("*** fault: iova=%08lx, flags=%d\n", iova, flags); > + pr_warn_ratelimited("*** fault: iova=%16lx, flags=%d\n", iova, flags); > return 0; > } > > -- > 2.7.4 > > _______________________________________________ > Freedreno mailing list > Freedreno@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/freedreno
On 07/05/2019 20:02, Jordan Crouse wrote: > When we move to 64 bit addressing for a5xx and a6xx targets we will start > seeing pagefaults at larger addresses so format them appropriately in the > log message for easier debugging. > > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > --- > > drivers/gpu/drm/msm/msm_iommu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c > index 12bb54c..1926329 100644 > --- a/drivers/gpu/drm/msm/msm_iommu.c > +++ b/drivers/gpu/drm/msm/msm_iommu.c > @@ -30,7 +30,7 @@ static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, > struct msm_iommu *iommu = arg; > if (iommu->base.handler) > return iommu->base.handler(iommu->base.arg, iova, flags); > - pr_warn_ratelimited("*** fault: iova=%08lx, flags=%d\n", iova, flags); > + pr_warn_ratelimited("*** fault: iova=%16lx, flags=%d\n", iova, flags); Why no leading 0 for 64-bit numbers? Will 32-bit platforms always get 8 useless characters? Regards.
On Thu, May 9, 2019 at 9:06 AM Marc Gonzalez <marc.w.gonzalez@free.fr> wrote: > > On 07/05/2019 20:02, Jordan Crouse wrote: > > > When we move to 64 bit addressing for a5xx and a6xx targets we will start > > seeing pagefaults at larger addresses so format them appropriately in the > > log message for easier debugging. > > > > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > > --- > > > > drivers/gpu/drm/msm/msm_iommu.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c > > index 12bb54c..1926329 100644 > > --- a/drivers/gpu/drm/msm/msm_iommu.c > > +++ b/drivers/gpu/drm/msm/msm_iommu.c > > @@ -30,7 +30,7 @@ static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, > > struct msm_iommu *iommu = arg; > > if (iommu->base.handler) > > return iommu->base.handler(iommu->base.arg, iova, flags); > > - pr_warn_ratelimited("*** fault: iova=%08lx, flags=%d\n", iova, flags); > > + pr_warn_ratelimited("*** fault: iova=%16lx, flags=%d\n", iova, flags); > > Why no leading 0 for 64-bit numbers? > > Will 32-bit platforms always get 8 useless characters? > well, they should be 0's, rather than garbage, if that was the question. I'm not sure how many hoops it is worth jumping thru to handle the diff between 32b GPU (<= a4xx) and 64b (>= a5xx). Even on newer devices, the display is still 32b iova. I guess this is *mostly* useful for debugging mesa (or at least I guess I'm the one who triggers the most iommu faults).. so maybe not worth caring about? BR, -R
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index 12bb54c..1926329 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -30,7 +30,7 @@ static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, struct msm_iommu *iommu = arg; if (iommu->base.handler) return iommu->base.handler(iommu->base.arg, iova, flags); - pr_warn_ratelimited("*** fault: iova=%08lx, flags=%d\n", iova, flags); + pr_warn_ratelimited("*** fault: iova=%16lx, flags=%d\n", iova, flags); return 0; }
When we move to 64 bit addressing for a5xx and a6xx targets we will start seeing pagefaults at larger addresses so format them appropriately in the log message for easier debugging. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> --- drivers/gpu/drm/msm/msm_iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)