| Message ID | 1572524473-19344-3-git-send-email-tdas@codeaurora.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add GPU & Video Clock controller driver for SC7180 | expand |
Quoting Taniya Das (2019-10-31 05:21:08) > diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml > new file mode 100644 > index 0000000..96aaf36 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml > @@ -0,0 +1,69 @@ > +# SPDX-License-Identifier: GPL-2.0-only Can it be GPL2 or BSD? I think Rob is asking for that sort of license on these files. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/bindings/clock/qcom,gpucc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Graphics Clock & Reset Controller Binding > + > +maintainers: > + - Taniya Das <tdas@codeaurora.org> > + > +description: | > + Qualcomm grpahics clock control module which supports the clocks, resets and > + power domains. > + > +properties: > + compatible: > + enum: > + - qcom,sdm845-gpucc > + - qcom,msm8998-gpucc Sort please.
On Tue, Nov 5, 2019 at 6:26 PM Stephen Boyd <sboyd@kernel.org> wrote: > > Quoting Taniya Das (2019-10-31 05:21:08) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml > > new file mode 100644 > > index 0000000..96aaf36 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml > > @@ -0,0 +1,69 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > Can it be GPL2 or BSD? I think Rob is asking for that sort of license on > these files. I do, but only on new bindings unless we determine relicensing is okay. Though here it doesn't look like much is copied over. > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/bindings/clock/qcom,gpucc.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Qualcomm Graphics Clock & Reset Controller Binding > > + > > +maintainers: > > + - Taniya Das <tdas@codeaurora.org> > > + > > +description: | > > + Qualcomm grpahics clock control module which supports the clocks, resets and > > + power domains. > > + > > +properties: > > + compatible: > > + enum: > > + - qcom,sdm845-gpucc > > + - qcom,msm8998-gpucc > > Sort please. When you get tired of telling people to do this we can make the tooling do it. :) Shouldn't be too hard. The majority of the work is probably fixing the existing cases that aren't sorted. Rob
diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt deleted file mode 100644 index 269afe8a..0000000 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt +++ /dev/null @@ -1,24 +0,0 @@ -Qualcomm Graphics Clock & Reset Controller Binding --------------------------------------------------- - -Required properties : -- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc" -- reg : shall contain base register location and length -- #clock-cells : from common clock binding, shall contain 1 -- #reset-cells : from common reset binding, shall contain 1 -- #power-domain-cells : from generic power domain binding, shall contain 1 -- clocks : shall contain the XO clock - shall contain the gpll0 out main clock (msm8998) -- clock-names : shall be "xo" - shall be "gpll0" (msm8998) - -Example: - gpucc: clock-controller@5090000 { - compatible = "qcom,sdm845-gpucc"; - reg = <0x5090000 0x9000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml new file mode 100644 index 0000000..96aaf36 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/qcom,gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller Binding + +maintainers: + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm grpahics clock control module which supports the clocks, resets and + power domains. + +properties: + compatible: + enum: + - qcom,sdm845-gpucc + - qcom,msm8998-gpucc + + clocks: + minItems: 1 + maxItems: 2 + items: + - description: Board XO source + - description: GPLL0 source from GCC + + clock-names: + minItems: 1 + maxItems: 2 + items: + - const: xo + - const: gpll0 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + # Example of GPUCC with clock node properties for SDM845: + - | + clock-controller@5090000 { + compatible = "qcom,sdm845-gpucc"; + reg = <0x5090000 0x9000>; + clocks = <&rpmhcc 0>, <&gcc 32>; + clock-names = "xo", "gpll0"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +...
The GPUCC clock provider have a bunch of generic properties that are needed in a device tree. Add a YAML schemas for those. Signed-off-by: Taniya Das <tdas@codeaurora.org> --- .../devicetree/bindings/clock/qcom,gpucc.txt | 24 -------- .../devicetree/bindings/clock/qcom,gpucc.yaml | 69 ++++++++++++++++++++++ 2 files changed, 69 insertions(+), 24 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc.txt create mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc.yaml -- Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.