diff mbox series

[v3,3/3] arm64: dts: msm8916: Add CCI node

Message ID 1583340776-27865-3-git-send-email-loic.poulain@linaro.org (mailing list archive)
State Superseded
Headers show
Series [v3,1/3] i2c: Add Qualcomm CCI I2C driver | expand

Commit Message

Loic Poulain March 4, 2020, 4:52 p.m. UTC
The msm8916 CCI controller provides one CCI/I2C bus.

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
---
 v2: add this patch in the series
 v3: add only cci node for now

 arch/arm64/boot/dts/qcom/msm8916.dtsi | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

Comments

Robert Foss March 4, 2020, 7:08 p.m. UTC | #1
Due to lack of suitable hardware, I currently can't test the msm8916,
but I have written similar DT nodes for the sdm845, which indeed work properly.

Signed-off-by: Robert Foss <robert.foss@linaro.org>

On Wed, 4 Mar 2020 at 17:49, Loic Poulain <loic.poulain@linaro.org> wrote:
>
> The msm8916 CCI controller provides one CCI/I2C bus.
>
> Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
> ---
>  v2: add this patch in the series
>  v3: add only cci node for now
>
>  arch/arm64/boot/dts/qcom/msm8916.dtsi | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> index 8686e10..985cb5f 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> @@ -1451,6 +1451,33 @@
>                         };
>                 };
>
> +               cci@1b0c000 {
> +                       compatible = "qcom,msm8916-cci";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0x1b0c000 0x1000>;
> +                       interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
> +                       clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
> +                               <&gcc GCC_CAMSS_CCI_AHB_CLK>,
> +                               <&gcc GCC_CAMSS_CCI_CLK>,
> +                               <&gcc GCC_CAMSS_AHB_CLK>;
> +                       clock-names = "camss_top_ahb", "cci_ahb",
> +                                     "cci", "camss_ahb";
> +                       assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
> +                                         <&gcc GCC_CAMSS_CCI_CLK>;
> +                       assigned-clock-rates = <80000000>, <19200000>;
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&cci0_default>;
> +                       status = "disabled";
> +
> +                       cci0: i2c-bus@0 {
> +                               reg = <0>;
> +                               clock-frequency = <400000>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                       };
> +               };
> +
>                 camss: camss@1b00000 {
>                         compatible = "qcom,msm8916-camss";
>                         reg = <0x1b0ac00 0x200>,
> --
> 2.7.4
>
Robert Foss March 4, 2020, 7:45 p.m. UTC | #2
I've had looked this too, and please ignore my sob, and feel free to add my r-b.

Reviewed-by: Robert Foss <robert.foss@linaro.org>

On Wed, 4 Mar 2020 at 20:08, Robert Foss <robert.foss@linaro.org> wrote:
>
> Due to lack of suitable hardware, I currently can't test the msm8916,
> but I have written similar DT nodes for the sdm845, which indeed work properly.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
>
> On Wed, 4 Mar 2020 at 17:49, Loic Poulain <loic.poulain@linaro.org> wrote:
> >
> > The msm8916 CCI controller provides one CCI/I2C bus.
> >
> > Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
> > ---
> >  v2: add this patch in the series
> >  v3: add only cci node for now
> >
> >  arch/arm64/boot/dts/qcom/msm8916.dtsi | 27 +++++++++++++++++++++++++++
> >  1 file changed, 27 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> > index 8686e10..985cb5f 100644
> > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> > @@ -1451,6 +1451,33 @@
> >                         };
> >                 };
> >
> > +               cci@1b0c000 {
> > +                       compatible = "qcom,msm8916-cci";
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +                       reg = <0x1b0c000 0x1000>;
> > +                       interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
> > +                       clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
> > +                               <&gcc GCC_CAMSS_CCI_AHB_CLK>,
> > +                               <&gcc GCC_CAMSS_CCI_CLK>,
> > +                               <&gcc GCC_CAMSS_AHB_CLK>;
> > +                       clock-names = "camss_top_ahb", "cci_ahb",
> > +                                     "cci", "camss_ahb";
> > +                       assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
> > +                                         <&gcc GCC_CAMSS_CCI_CLK>;
> > +                       assigned-clock-rates = <80000000>, <19200000>;
> > +                       pinctrl-names = "default";
> > +                       pinctrl-0 = <&cci0_default>;
> > +                       status = "disabled";
> > +
> > +                       cci0: i2c-bus@0 {
> > +                               reg = <0>;
> > +                               clock-frequency = <400000>;
> > +                               #address-cells = <1>;
> > +                               #size-cells = <0>;
> > +                       };
> > +               };
> > +
> >                 camss: camss@1b00000 {
> >                         compatible = "qcom,msm8916-camss";
> >                         reg = <0x1b0ac00 0x200>,
> > --
> > 2.7.4
> >
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 8686e10..985cb5f 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -1451,6 +1451,33 @@ 
 			};
 		};
 
+		cci@1b0c000 {
+			compatible = "qcom,msm8916-cci";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x1b0c000 0x1000>;
+			interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+				<&gcc GCC_CAMSS_CCI_AHB_CLK>,
+				<&gcc GCC_CAMSS_CCI_CLK>,
+				<&gcc GCC_CAMSS_AHB_CLK>;
+			clock-names = "camss_top_ahb", "cci_ahb",
+				      "cci", "camss_ahb";
+			assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
+					  <&gcc GCC_CAMSS_CCI_CLK>;
+			assigned-clock-rates = <80000000>, <19200000>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&cci0_default>;
+			status = "disabled";
+
+			cci0: i2c-bus@0 {
+				reg = <0>;
+				clock-frequency = <400000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
 		camss: camss@1b00000 {
 			compatible = "qcom,msm8916-camss";
 			reg = <0x1b0ac00 0x200>,