Message ID | 1590582292-13314-6-git-send-email-sivaprak@codeaurora.org (mailing list archive) |
---|---|
State | Superseded |
Headers | show |
Series | Add APSS clock controller support for IPQ6018 | expand |
Quoting Sivaprakash Murugesan (2020-05-27 05:24:52) > Enable apss pll support. > > Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> > --- > [V6] > * split the mailbox driver from this patch > arch/arm64/boot/dts/qcom/ipq6018.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi > index 1aa8d85..3956e44 100644 > --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi > @@ -300,6 +300,14 @@ > #mbox-cells = <1>; > }; > > + apsspll: clock@b116000 { > + compatible = "qcom,ipq6018-a53pll"; > + reg = <0x0b116000 0x40>; > + #clock-cells = <0>; > + clocks = <&xo>; > + clock-names = "xo"; > + }; > + I'd expect to see this inside an soc node. Also this doesn't go via clk tree so don't send it with the clk patches. > timer { > compatible = "arm,armv8-timer"; > interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 1aa8d85..3956e44 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -300,6 +300,14 @@ #mbox-cells = <1>; }; + apsspll: clock@b116000 { + compatible = "qcom,ipq6018-a53pll"; + reg = <0x0b116000 0x40>; + #clock-cells = <0>; + clocks = <&xo>; + clock-names = "xo"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
Enable apss pll support. Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> --- [V6] * split the mailbox driver from this patch arch/arm64/boot/dts/qcom/ipq6018.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)