| Message ID | 1591691846-7578-3-git-send-email-ppvk@codeaurora.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 557ed5f06c63fc6dc37847ad299c4fb77aa90015 |
| Headers | show |
| Series | Add SDHC interconnect bandwidth scaling | expand |
On Tue, 9 Jun 2020 at 10:38, Pradeep P V K <ppvk@codeaurora.org> wrote: > > Add interconnect bandwidth scaling supported strings for qcom-sdhci > controller. > > Signed-off-by: Pradeep P V K <ppvk@codeaurora.org> > Acked-by: Rob Herring <robh@kernel.org> > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Applied for next, thanks! Kind regards Uffe > --- > Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt > index b8e1d2b..3b602fd 100644 > --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt > +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt > @@ -54,6 +54,21 @@ Required properties: > - qcom,dll-config: Chipset and Platform specific value. Use this field to > specify the DLL_CONFIG register value as per Hardware Programming Guide. > > +Optional Properties: > +* Following bus parameters are required for interconnect bandwidth scaling: > +- interconnects: Pairs of phandles and interconnect provider specifier > + to denote the edge source and destination ports of > + the interconnect path. > + > +- interconnect-names: For sdhc, we have two main paths. > + 1. Data path : sdhc to ddr > + 2. Config path : cpu to sdhc > + For Data interconnect path the name supposed to be > + is "sdhc-ddr" and for config interconnect path it is > + "cpu-sdhc". > + Please refer to Documentation/devicetree/bindings/ > + interconnect/ for more details. > + > Example: > > sdhc_1: sdhci@f9824900 { > @@ -71,6 +86,9 @@ Example: > > clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; > clock-names = "core", "iface"; > + interconnects = <&qnoc MASTER_SDCC_ID &qnoc SLAVE_DDR_ID>, > + <&qnoc MASTER_CPU_ID &qnoc SLAVE_SDCC_ID>; > + interconnect-names = "sdhc-ddr","cpu-sdhc"; > > qcom,dll-config = <0x000f642c>; > qcom,ddr-config = <0x80040868>; > -- > 1.9.1 >
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt index b8e1d2b..3b602fd 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt @@ -54,6 +54,21 @@ Required properties: - qcom,dll-config: Chipset and Platform specific value. Use this field to specify the DLL_CONFIG register value as per Hardware Programming Guide. +Optional Properties: +* Following bus parameters are required for interconnect bandwidth scaling: +- interconnects: Pairs of phandles and interconnect provider specifier + to denote the edge source and destination ports of + the interconnect path. + +- interconnect-names: For sdhc, we have two main paths. + 1. Data path : sdhc to ddr + 2. Config path : cpu to sdhc + For Data interconnect path the name supposed to be + is "sdhc-ddr" and for config interconnect path it is + "cpu-sdhc". + Please refer to Documentation/devicetree/bindings/ + interconnect/ for more details. + Example: sdhc_1: sdhci@f9824900 { @@ -71,6 +86,9 @@ Example: clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; clock-names = "core", "iface"; + interconnects = <&qnoc MASTER_SDCC_ID &qnoc SLAVE_DDR_ID>, + <&qnoc MASTER_CPU_ID &qnoc SLAVE_SDCC_ID>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; qcom,dll-config = <0x000f642c>; qcom,ddr-config = <0x80040868>;