| Message ID | 1594877570-9280-1-git-send-email-sivaprak@codeaurora.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 044f507dc0a3070985592d84707a9d69746d84c6 |
| Headers | show |
| Series | clk: qcom: ipq8074: Add correct index for PCIe clocks | expand |
Quoting Sivaprakash Murugesan (2020-07-15 22:32:50) > The PCIe clocks GCC_PCIE0_AXI_S_BRIDGE_CLK, GCC_PCIE0_RCHNG_CLK_SRC, > GCC_PCIE0_RCHNG_CLK are wrongly added to the gcc reset group. > > Move them to the gcc clock group. > > Reported-by: kernel test robot <lkp@intel.com> > Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> > --- Applied to clk-next
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h index e3e018565add..8e2bec1c91bf 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h @@ -230,6 +230,9 @@ #define GCC_GP1_CLK 221 #define GCC_GP2_CLK 222 #define GCC_GP3_CLK 223 +#define GCC_PCIE0_AXI_S_BRIDGE_CLK 224 +#define GCC_PCIE0_RCHNG_CLK_SRC 225 +#define GCC_PCIE0_RCHNG_CLK 226 #define GCC_BLSP1_BCR 0 #define GCC_BLSP1_QUP1_BCR 1 @@ -363,8 +366,5 @@ #define GCC_PCIE1_AHB_ARES 129 #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131 -#define GCC_PCIE0_AXI_S_BRIDGE_CLK 132 -#define GCC_PCIE0_RCHNG_CLK_SRC 133 -#define GCC_PCIE0_RCHNG_CLK 134 #endif
The PCIe clocks GCC_PCIE0_AXI_S_BRIDGE_CLK, GCC_PCIE0_RCHNG_CLK_SRC, GCC_PCIE0_RCHNG_CLK are wrongly added to the gcc reset group. Move them to the gcc clock group. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> --- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)