From patchwork Tue Aug 25 02:03:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 11734701 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AD9771575 for ; Tue, 25 Aug 2020 02:05:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9770B20738 for ; Tue, 25 Aug 2020 02:05:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="ChZ+3hCf" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726998AbgHYCEu (ORCPT ); Mon, 24 Aug 2020 22:04:50 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:32601 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726828AbgHYCEt (ORCPT ); Mon, 24 Aug 2020 22:04:49 -0400 X-UUID: 844028df7fe74880b1268a499b1a961e-20200825 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=FJjaeYDfj7zaJAqd4TVOuDNqHaL59TRiYSGWfzunuhk=; b=ChZ+3hCfveHcwZKGN7XULE1WViMVxpQ2l0v3FKmquAr8SwOElZJ0ZpLFzhaueG8vsGlOlcMX+QOP6jMzirkMvASBPSAcjuG6ptKimuEAb5jX+2iRlm4GwUlWTKl1DKa2Dc1S8cXkkf7C0lFYDyCdIvTKKWCUAbwAdDN3cYbrMuc=; X-UUID: 844028df7fe74880b1268a499b1a961e-20200825 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 965857563; Tue, 25 Aug 2020 10:04:45 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS31DR.mediatek.inc (172.27.6.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 25 Aug 2020 10:04:41 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 25 Aug 2020 10:04:43 +0800 From: Chunfeng Yun To: Kishon Vijay Abraham I CC: Vinod Koul , Andy Gross , Bjorn Andersson , Matthias Brugger , Chunfeng Yun , Rikard Falkeborn , Bharat Gooty , Rayagonda Kokatanur , , , , Subject: [PATCH 6/6] phy: phy-pxa-28nm-usb2: convert to readl_poll_timeout() Date: Tue, 25 Aug 2020 10:03:07 +0800 Message-ID: <1598320987-25518-6-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1598320987-25518-1-git-send-email-chunfeng.yun@mediatek.com> References: <1598320987-25518-1-git-send-email-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 4B7CA52755C8D266865A594E4B03F79BCD596B20C172F3EC76907D9CF8D018632000:8 X-MTK: N Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use readl_poll_timeout() to simplify code Signed-off-by: Chunfeng Yun --- drivers/phy/marvell/phy-pxa-28nm-usb2.c | 33 +++++++++++++++------------------ 1 file changed, 15 insertions(+), 18 deletions(-) diff --git a/drivers/phy/marvell/phy-pxa-28nm-usb2.c b/drivers/phy/marvell/phy-pxa-28nm-usb2.c index 9fd8817..a175ae9 100644 --- a/drivers/phy/marvell/phy-pxa-28nm-usb2.c +++ b/drivers/phy/marvell/phy-pxa-28nm-usb2.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -138,15 +139,12 @@ struct mv_usb2_phy { struct clk *clk; }; -static bool wait_for_reg(void __iomem *reg, u32 mask, unsigned long timeout) +static int wait_for_reg(void __iomem *reg, u32 mask, u32 ms) { - timeout += jiffies; - while (time_is_after_eq_jiffies(timeout)) { - if ((readl(reg) & mask) == mask) - return true; - msleep(1); - } - return false; + u32 val; + + return readl_poll_timeout(reg, val, ((val & mask) == mask), + 1000, 1000 * ms); } static int mv_usb2_phy_28nm_init(struct phy *phy) @@ -208,24 +206,23 @@ static int mv_usb2_phy_28nm_init(struct phy *phy) */ /* Make sure PHY Calibration is ready */ - if (!wait_for_reg(base + PHY_28NM_CAL_REG, - PHY_28NM_PLL_PLLCAL_DONE | PHY_28NM_PLL_IMPCAL_DONE, - HZ / 10)) { + ret = wait_for_reg(base + PHY_28NM_CAL_REG, + PHY_28NM_PLL_PLLCAL_DONE | PHY_28NM_PLL_IMPCAL_DONE, + 100); + if (ret) { dev_warn(&pdev->dev, "USB PHY PLL calibrate not done after 100mS."); - ret = -ETIMEDOUT; goto err_clk; } - if (!wait_for_reg(base + PHY_28NM_RX_REG1, - PHY_28NM_RX_SQCAL_DONE, HZ / 10)) { + ret = wait_for_reg(base + PHY_28NM_RX_REG1, + PHY_28NM_RX_SQCAL_DONE, 100); + if (ret) { dev_warn(&pdev->dev, "USB PHY RX SQ calibrate not done after 100mS."); - ret = -ETIMEDOUT; goto err_clk; } /* Make sure PHY PLL is ready */ - if (!wait_for_reg(base + PHY_28NM_PLL_REG0, - PHY_28NM_PLL_READY, HZ / 10)) { + ret = wait_for_reg(base + PHY_28NM_PLL_REG0, PHY_28NM_PLL_READY, 100); + if (ret) { dev_warn(&pdev->dev, "PLL_READY not set after 100mS."); - ret = -ETIMEDOUT; goto err_clk; }