From patchwork Tue Oct 13 05:15:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan T X-Patchwork-Id: 11834961 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C42BA1580 for ; Tue, 13 Oct 2020 05:15:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9A8C1208B8 for ; Tue, 13 Oct 2020 05:15:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="TDorqUE3" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732353AbgJMFP4 (ORCPT ); Tue, 13 Oct 2020 01:15:56 -0400 Received: from m42-4.mailgun.net ([69.72.42.4]:26039 "EHLO m42-4.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732344AbgJMFP4 (ORCPT ); Tue, 13 Oct 2020 01:15:56 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1602566155; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=mLzptLEzGt3ap5c0T2QJDDwVUFSR6Rbgs8XlUGD7pbo=; b=TDorqUE3uSCSi4K0ZGgCHMlnqTHYFdyw4KT4zE1h879GqEcJV2URnzDPoF+b8rPCmGjrZss2 PhGY/zseTFVKIzIHBYxz+8pcUQ3o8tkpSy5NBkS/Pld5a4qvwNQ045pOQg9PuO4N21CXmEje mF4KotAfJY0F9pQ5U6idDppF528= X-Mailgun-Sending-Ip: 69.72.42.4 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n06.prod.us-west-2.postgun.com with SMTP id 5f85380b06d81bc48dd23fbf (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Tue, 13 Oct 2020 05:15:55 GMT Sender: kathirav=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 28B84C43387; Tue, 13 Oct 2020 05:15:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=ALL_TRUSTED,BAYES_00,SPF_FAIL, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from kathirav-linux.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: kathirav) by smtp.codeaurora.org (Postfix) with ESMTPSA id 3D47CC433CB; Tue, 13 Oct 2020 05:15:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 3D47CC433CB Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=kathirav@codeaurora.org From: Kathiravan T To: agross@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh+dt@kernel.org, sivaprak@codeaurora.org, peter.ujfalusi@ti.com, boris.brezillon@collabora.com, linux-arm-msm@vger.kernel.org, linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: kathirav@codeaurora.org, Anusha Canchi Ramachandra Rao Subject: [PATCH 3/3] arm64: dts: ipq6018: Add the QPIC peripheral nodes Date: Tue, 13 Oct 2020 10:45:24 +0530 Message-Id: <1602566124-13456-4-git-send-email-kathirav@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1602566124-13456-1-git-send-email-kathirav@codeaurora.org> References: <1602566124-13456-1-git-send-email-kathirav@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the QPIC BAM and QPIC NAND controller support and enable the same in board DTS file. Co-developed-by: Anusha Canchi Ramachandra Rao Signed-off-by: Anusha Canchi Ramachandra Rao Signed-off-by: Kathiravan T --- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 16 ++++++++ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 41 ++++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index b31117a93995..6e68de1a0b0a 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -62,3 +62,19 @@ spi_0_pins: spi-0-pins { bias-pull-down; }; }; + +&qpic_bam { + status = "ok"; +}; + +&qpic_nand { + status = "ok"; + + nand@0 { + reg = <0>; + + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 1aa8d8579463..6b13e390ee29 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -173,6 +173,17 @@ serial_3_pins: serial3-pinmux { drive-strength = <8>; bias-pull-down; }; + + qpic_pins: qpic-pins { + pins = "gpio1", "gpio3", "gpio4", + "gpio5", "gpio6", "gpio7", + "gpio8", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", + "gpio15", "gpio17"; + function = "qpic_pad"; + drive-strength = <8>; + bias-disable; + }; }; gcc: gcc@1800000 { @@ -274,6 +285,36 @@ i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */ status = "disabled"; }; + qpic_bam: dma@7984000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07984000 0x1a000>; + interrupts = ; + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "iface_clk", "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + qpic_nand: nand@79b0000 { + compatible = "qcom,ipq6018-nand"; + reg = <0x079b0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "core", "aon"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + pinctrl-0 = <&qpic_pins>; + pinctrl-names = "default"; + status = "disabled"; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; interrupt-controller;