diff mbox series

bus: mhi: Ensure correct ring update ordering with memory barrier

Message ID 1605867751-22819-1-git-send-email-loic.poulain@linaro.org (mailing list archive)
State Superseded
Headers show
Series bus: mhi: Ensure correct ring update ordering with memory barrier | expand

Commit Message

Loic Poulain Nov. 20, 2020, 10:22 a.m. UTC
The ring element data, though being part of coherent memory, still need
to be performed before updating the ring context to point to this new
element. That can be guaranteed with a memory barrier (dma_wmb).

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
---
 drivers/bus/mhi/core/main.c | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Jeffrey Hugo Nov. 25, 2020, 5:46 p.m. UTC | #1
On 11/20/2020 3:22 AM, Loic Poulain wrote:
> The ring element data, though being part of coherent memory, still need
> to be performed before updating the ring context to point to this new
> element. That can be guaranteed with a memory barrier (dma_wmb).
> 
> Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
> ---
>   drivers/bus/mhi/core/main.c | 6 ++++++
>   1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/bus/mhi/core/main.c b/drivers/bus/mhi/core/main.c
> index 94be0f8..188501c0 100644
> --- a/drivers/bus/mhi/core/main.c
> +++ b/drivers/bus/mhi/core/main.c
> @@ -111,7 +111,13 @@ void mhi_ring_chan_db(struct mhi_controller *mhi_cntrl,
>   	dma_addr_t db;
>   
>   	db = ring->iommu_base + (ring->wp - ring->base);
> +
> +	/* Writes to the new ring element must be visible to the hardware
> +	 * before letting h/w know there is new element to fetch.
> +	 */

This doesn't look like the correct style for multi-line comments.

> +	dma_wmb();
>   	*ring->ctxt_wp = db;
> +
>   	mhi_chan->db_cfg.process_db(mhi_cntrl, &mhi_chan->db_cfg,
>   				    ring->db_addr, db);
>   }
>
diff mbox series

Patch

diff --git a/drivers/bus/mhi/core/main.c b/drivers/bus/mhi/core/main.c
index 94be0f8..188501c0 100644
--- a/drivers/bus/mhi/core/main.c
+++ b/drivers/bus/mhi/core/main.c
@@ -111,7 +111,13 @@  void mhi_ring_chan_db(struct mhi_controller *mhi_cntrl,
 	dma_addr_t db;
 
 	db = ring->iommu_base + (ring->wp - ring->base);
+
+	/* Writes to the new ring element must be visible to the hardware
+	 * before letting h/w know there is new element to fetch.
+	 */
+	dma_wmb();
 	*ring->ctxt_wp = db;
+
 	mhi_chan->db_cfg.process_db(mhi_cntrl, &mhi_chan->db_cfg,
 				    ring->db_addr, db);
 }