| Message ID | 1606198876-3515-2-git-send-email-sibis@codeaurora.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 3c9c31c2523ecd5b609a2eecb5ad524ef4fc931c |
| Headers | show |
| Series | [v2,1/2] arm64: dts: qcom: sc7180-lite: Tweak DDR/L3 scaling on SC7180-lite | expand |
Hi, On Mon, Nov 23, 2020 at 10:21 PM Sibi Sankar <sibis@codeaurora.org> wrote: > > Add DDR/L3 bandwidth votes for the pro variant of SC7180 SoC, as it support > frequencies upto 2.5 GHz. > > Signed-off-by: Sibi Sankar <sibis@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/sc7180.dtsi | 5 +++++ > 1 file changed, 5 insertions(+) Reviewed-by: Douglas Anderson <dianders@chromium.org>
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 625e922c273d..05bc10a4c84d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -527,6 +527,11 @@ opp-hz = /bits/ 64 <2400000000>; opp-peak-kBps = <8532000 23347200>; }; + + cpu6_opp16: opp-2553600000 { + opp-hz = /bits/ 64 <2553600000>; + opp-peak-kBps = <8532000 23347200>; + }; }; memory@80000000 {
Add DDR/L3 bandwidth votes for the pro variant of SC7180 SoC, as it support frequencies upto 2.5 GHz. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 5 +++++ 1 file changed, 5 insertions(+)