From patchwork Wed Mar 3 12:17:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 12114339 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 764E7C28E87 for ; Wed, 3 Mar 2021 21:42:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5D2BC64EFD for ; Wed, 3 Mar 2021 21:42:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1389512AbhCCVim (ORCPT ); Wed, 3 Mar 2021 16:38:42 -0500 Received: from m42-2.mailgun.net ([69.72.42.2]:41661 "EHLO m42-2.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348585AbhCCMWK (ORCPT ); Wed, 3 Mar 2021 07:22:10 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1614774102; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=DzLkI4a0qpXfTSCIeOShPYXIAGCZl9s8dzOC36cEvU8=; b=k34pKC6GjSgyx/kt4YH7UvTq5QZvsWm1GMZomX/5viup5f8cz4iKq/GQEtcBG+NhYHbw7lZZ wkhWq2EbbHE2WX6f+Y1SOV6hVfkmYjISgY3ygztxdTuYDheokyqmMCKk2grvh5alcIIMGlrG 2H7yLJ3G5EDJVgfOi3iWWFqZ89U= X-Mailgun-Sending-Ip: 69.72.42.2 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n01.prod.us-west-2.postgun.com with SMTP id 603f7f380071502ba9b5febe (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Wed, 03 Mar 2021 12:21:12 GMT Sender: rnayak=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 66642C43461; Wed, 3 Mar 2021 12:21:12 +0000 (UTC) Received: from blr-ubuntu-173.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: rnayak) by smtp.codeaurora.org (Postfix) with ESMTPSA id B59D0C43463; Wed, 3 Mar 2021 12:21:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B59D0C43463 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, swboyd@chromium.org, Rajendra Nayak Subject: [PATCH v2 03/14] arm64: dts: sc7280: Add basic dts/dtsi files for sc7280 soc Date: Wed, 3 Mar 2021 17:47:47 +0530 Message-Id: <1614773878-8058-4-git-send-email-rnayak@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1614773878-8058-1-git-send-email-rnayak@codeaurora.org> References: <1614773878-8058-1-git-send-email-rnayak@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add initial device tree support for the sc7280 SoC and the IDP boards based on this SoC Signed-off-by: Rajendra Nayak Reviewed-by: Stephen Boyd --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sc7280-idp.dts | 47 +++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 299 ++++++++++++++++++++++++++++++++ 3 files changed, 347 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7280.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 549a7a2..54cd8ea 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -40,6 +40,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-kb.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts new file mode 100644 index 0000000..950ecb2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * sc7280 IDP board device tree source + * + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include "sc7280.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. sc7280 IDP platform"; + compatible = "qcom,sc7280-idp", "qcom,sc7280"; + + aliases { + serial0 = &uart5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +/* PINCTRL - additions to nodes defined in sc7280.dtsi */ + +&qup_uart5_default { + tx { + pins = "gpio46"; + drive-strength = <2>; + bias-disable; + }; + + rx { + pins = "gpio47"; + drive-strength = <2>; + bias-pull-up; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi new file mode 100644 index 0000000..4a56d9c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * sc7280 SoC device tree source + * + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,kryo"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,kryo"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "arm,kryo"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "arm,kryo"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "arm,kryo"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "arm,kryo"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + + firmware { + scm { + compatible = "qcom,scm-sc7280", "qcom,scm"; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sc7280"; + reg = <0 0x00100000 0 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + qupv3_id_0: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x009c0000 0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart5: serial@994000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x00994000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart5_default>; + interrupts = ; + status = "disabled"; + }; + }; + + tlmm: pinctrl@f100000 { + compatible = "qcom,sc7280-pinctrl"; + reg = <0 0x0f100000 0 0x1000000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 175>; + + qup_uart5_default: qup-uart5-default { + pins = "gpio46", "gpio47"; + function = "qup13"; + }; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0 0x17a00000 0 0x10000>, /* GICD */ + <0 0x17a60000 0 0x100000>; /* GICR * 8 */ + interrupts = ; + + gic-its@17a40000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0 0x17a40000 0 0x20000>; + status = "disabled"; + }; + }; + + timer@17c20000 { + #address-cells = <2>; + #size-cells = <2>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0 0x17c20000 0 0x1000>; + + frame@17c21000 { + frame-number = <0>; + interrupts = , + ; + reg = <0 0x17c21000 0 0x1000>, + <0 0x17c22000 0 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = ; + reg = <0 0x17c23000 0 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = ; + reg = <0 0x17c25000 0 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = ; + reg = <0 0x17c27000 0 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = ; + reg = <0 0x17c29000 0 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = ; + reg = <0 0x17c2b000 0 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = ; + reg = <0 0x17c2d000 0 0x1000>; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +};