[v13,4/4] dt-bindings: msm/dp: Add bindings of MSM DisplayPort controller

Commit Message

Krishna Manikandan March 5, 2021, 1:29 p.m. UTC

Add bindings for Snapdragon DisplayPort controller driver.

Signed-off-by: Chandan Uddaraju <[e-mail]>
Signed-off-by: Vara Reddy <[e-mail]>
Signed-off-by: Tanmay Shah <[e-mail]>
Signed-off-by: Kuogee Hsieh <[e-mail]>
Signed-off-by: Krishna Manikandan <[e-mail]>

Changes in V2:
-Provide details about sel-gpio

Changes in V4:
-Provide details about max dp lanes
-Change the commit text

Changes in V5:
-moved dp.txt to yaml file

Changes in v6:
- Squash all AUX LUT properties into one pattern Property
- Make aux-cfg[0-9]-settings properties optional
- Remove PLL/PHY bindings from DP controller dts
- Add DP clocks description
- Remove _clk suffix from clock names
- Rename pixel clock to stream_pixel
- Remove redundant bindings (GPIO, PHY, HDCP clock, etc..)
- Fix indentation
- Add Display Port as interface of DPU in DPU bindings
  and add port mapping accordingly.

Chages in v7:
- Add dp-controller.yaml file common between multiple SOC
- Rename dp-sc7180.yaml to dp-controller-sc7180.yaml
- change compatible string and add SOC name to it.
- Remove Root clock generator for pixel clock
- Add assigned-clocks and assigned-clock-parents bindings
- Remove redundant properties, descriptions and blank lines
- Add DP port in DPU bindings
- Update depends-on tag in commit message and rebase change accordingly

Changes in v8:
- Add MDSS AHB clock in bindings

Changes in v9:
- Remove redundant reg-name property
- Change assigned-clocks and assigned-clocks-parents counts to 2
- Use IRQ flags in example dts

Changes in v10:
- Change title of this patch as it does not contain PLL bindings anymore
- Remove redundant properties
- Remove use of IRQ flag
- Fix ports property

Changes in v11:
- add ports required of both #address-cells and  #size-cells
- add required operating-points-v2
- add required #sound-dai-cells
- add required power-domains
- update maintainer list

Changes in v12:
- remove soc node from examples (Stephen Boyd)
- split dpu-sc7180.yaml changes to separate patch (Stephen Boyd)
---
 .../bindings/display/msm/dp-controller.yaml        | 147 +++++++++++++++++++++
 1 file changed, 147 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/msm/dp-controller.yaml

Comments

Stephen Boyd March 13, 2021, 10:41 p.m. UTC | #1

Quoting Krishna Manikandan (2021-03-05 05:29:12)
> Add bindings for Snapdragon DisplayPort controller driver.
> 
> Signed-off-by: Chandan Uddaraju <[e-mail]>
> Signed-off-by: Vara Reddy <[e-mail]>
> Signed-off-by: Tanmay Shah <[e-mail]>
> Signed-off-by: Kuogee Hsieh <[e-mail]>
> Signed-off-by: Krishna Manikandan <[e-mail]>
> 
> Changes in V2:
> -Provide details about sel-gpio
> 
> Changes in V4:
> -Provide details about max dp lanes
> -Change the commit text
> 
> Changes in V5:
> -moved dp.txt to yaml file
> 
> Changes in v6:
> - Squash all AUX LUT properties into one pattern Property
> - Make aux-cfg[0-9]-settings properties optional
> - Remove PLL/PHY bindings from DP controller dts
> - Add DP clocks description
> - Remove _clk suffix from clock names
> - Rename pixel clock to stream_pixel
> - Remove redundant bindings (GPIO, PHY, HDCP clock, etc..)
> - Fix indentation
> - Add Display Port as interface of DPU in DPU bindings
>   and add port mapping accordingly.
> 
> Chages in v7:
> - Add dp-controller.yaml file common between multiple SOC
> - Rename dp-sc7180.yaml to dp-controller-sc7180.yaml
> - change compatible string and add SOC name to it.
> - Remove Root clock generator for pixel clock
> - Add assigned-clocks and assigned-clock-parents bindings
> - Remove redundant properties, descriptions and blank lines
> - Add DP port in DPU bindings
> - Update depends-on tag in commit message and rebase change accordingly
> 
> Changes in v8:
> - Add MDSS AHB clock in bindings
> 
> Changes in v9:
> - Remove redundant reg-name property
> - Change assigned-clocks and assigned-clocks-parents counts to 2
> - Use IRQ flags in example dts
> 
> Changes in v10:
> - Change title of this patch as it does not contain PLL bindings anymore
> - Remove redundant properties
> - Remove use of IRQ flag
> - Fix ports property
> 
> Changes in v11:
> - add ports required of both #address-cells and  #size-cells
> - add required operating-points-v2
> - add required #sound-dai-cells
> - add required power-domains
> - update maintainer list
> 
> Changes in v12:
> - remove soc node from examples (Stephen Boyd)
> - split dpu-sc7180.yaml changes to separate patch (Stephen Boyd)
> ---

Reviewed-by: Stephen Boyd <[e-mail]>

Dmitry Baryshkov March 14, 2021, 1:28 p.m. UTC | #2

On 05/03/2021 16:29, Krishna Manikandan wrote:
> Add bindings for Snapdragon DisplayPort controller driver.
> 
> Signed-off-by: Chandan Uddaraju <[e-mail]>
> Signed-off-by: Vara Reddy <[e-mail]>
> Signed-off-by: Tanmay Shah <[e-mail]>
> Signed-off-by: Kuogee Hsieh <[e-mail]>
> Signed-off-by: Krishna Manikandan <[e-mail]>

Krishna, Stephen, I've a question basing on our experiments with the DP 
on sm8250.
Which driver will reparent dispcc's DP clocks to the DP_PHY clocks?

We can do this using the assigned-clocks-parents either in the dispcc or 
in the DP nodes. Which would be preferable?

Kuogee Hsieh March 16, 2021, 4:45 p.m. UTC | #3

On 2021-03-14 06:28, Dmitry Baryshkov wrote:
> On 05/03/2021 16:29, Krishna Manikandan wrote:
>> Add bindings for Snapdragon DisplayPort controller driver.
>> 
>> Signed-off-by: Chandan Uddaraju <[e-mail]>
>> Signed-off-by: Vara Reddy <[e-mail]>
>> Signed-off-by: Tanmay Shah <[e-mail]>
>> Signed-off-by: Kuogee Hsieh <[e-mail]>
>> Signed-off-by: Krishna Manikandan <[e-mail]>
> 
> Krishna, Stephen, I've a question basing on our experiments with the
> DP on sm8250.
> Which driver will reparent dispcc's DP clocks to the DP_PHY clocks?
> 
> We can do this using the assigned-clocks-parents either in the dispcc
> or in the DP nodes. Which would be preferable?
at sc7180.dtsi, it is done at DP node

Dmitry Baryshkov March 16, 2021, 5:19 p.m. UTC | #4

On 16/03/2021 19:45, [e-mail] wrote:
> On 2021-03-14 06:28, Dmitry Baryshkov wrote:
>> On 05/03/2021 16:29, Krishna Manikandan wrote:
>>> Add bindings for Snapdragon DisplayPort controller driver.
>>>
>>> Signed-off-by: Chandan Uddaraju <[e-mail]>
>>> Signed-off-by: Vara Reddy <[e-mail]>
>>> Signed-off-by: Tanmay Shah <[e-mail]>
>>> Signed-off-by: Kuogee Hsieh <[e-mail]>
>>> Signed-off-by: Krishna Manikandan <[e-mail]>
>>
>> Krishna, Stephen, I've a question basing on our experiments with the
>> DP on sm8250.
>> Which driver will reparent dispcc's DP clocks to the DP_PHY clocks?
>>
>> We can do this using the assigned-clocks-parents either in the dispcc
>> or in the DP nodes. Which would be preferable?
> at sc7180.dtsi, it is done at DP node

Could you please add those lines to the dtsi example you are providing?

Patch

diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
new file mode 100644
index 0000000..38d8a96
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -0,0 +1,147 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MSM Display Port Controller
+
+maintainers:
+  - Kuogee Hsieh <[e-mail]>
+
+description: |
+  Device tree bindings for DisplayPort host controller for MSM targets
+  that are compatible with VESA DisplayPort interface specification.
+
+properties:
+  compatible:
+    enum:
+      - qcom,sc7180-dp
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: AHB clock to enable register access
+      - description: Display Port AUX clock
+      - description: Display Port Link clock
+      - description: Link interface clock between DP and PHY
+      - description: Display Port Pixel clock
+
+  clock-names:
+    items:
+      - const: core_iface
+      - const: core_aux
+      - const: ctrl_link
+      - const: ctrl_link_iface
+      - const: stream_pixel
+
+  phys:
+    maxItems: 1
+
+  phy-names:
+    items:
+      - const: dp
+
+  operating-points-v2:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  "#sound-dai-cells":
+    const: 0
+
+  ports:
+    type: object
+    description: |
+      A ports node with endpoint definitions as defined in
+      Documentation/devicetree/bindings/media/video-interfaces.txt.
+    properties:
+      "#address-cells":
+        const: 1
+
+      "#size-cells":
+        const: 0
+
+      port@0:
+        type: object
+        description: Input endpoint of the controller
+
+      port@1:
+        type: object
+        description: Output endpoint of the controller
+
+    required:
+      - "#address-cells"
+      - "#size-cells"
+
+    additionalProperties: false
+
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - phys
+  - phy-names
+  - "#sound-dai-cells"
+  - power-domains
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
+    #include <dt-bindings/power/qcom-aoss-qmp.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
+
+    displayport-controller@ae90000 {
+        compatible = "qcom,sc7180-dp";
+        reg = <0xae90000 0x1400>;
+        interrupt-parent = <&mdss>;
+        interrupts = <12>;
+        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+                 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+                 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+                 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+        clock-names = "core_iface", "core_aux",
+                      "ctrl_link",
+                      "ctrl_link_iface", "stream_pixel";
+
+        phys = <&dp_phy>;
+        phy-names = "dp";
+
+        #sound-dai-cells = <0>;
+
+        power-domains = <&rpmhpd SC7180_CX>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+                endpoint {
+                    remote-endpoint = <&dpu_intf0_out>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+                endpoint {
+                    remote-endpoint = <&typec>;
+                };
+            };
+        };
+    };
+...