| Message ID | 1629282424-4070-1-git-send-email-mkrishn@codeaurora.org (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [v1,1/4] dt-bindings: msm: add DT bindings for sc7280 | expand |
On Wed, 18 Aug 2021 15:57:01 +0530, Krishna Manikandan wrote: > MSM Mobile Display Subsystem (MDSS) encapsulates sub-blocks > like DPU display controller, DSI, EDP etc. Add required DPU > device tree bindings for SC7280. > > Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org> > --- > .../bindings/display/msm/dpu-sc7280.yaml | 228 +++++++++++++++++++++ > 1 file changed, 228 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/display/msm/dpu-sc7280.example.dts:19:18: fatal error: dt-bindings/clock/qcom,dispcc-sc7280.h: No such file or directory 19 | #include <dt-bindings/clock/qcom,dispcc-sc7280.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:380: Documentation/devicetree/bindings/display/msm/dpu-sc7280.example.dt.yaml] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1419: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/1517976 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
Quoting Krishna Manikandan (2021-08-18 03:27:01) > diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml > new file mode 100644 > index 0000000..3d256c0 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml > @@ -0,0 +1,228 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/dpu-sc7280.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Display DPU dt properties for SC7280 target Drop "target"? > + > +maintainers: > + - Krishna Manikandan <mkrishn@codeaurora.org> > + > +description: | > + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates Space after Subsystem please. > + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree > + bindings of MDSS and DPU are mentioned for SC7280 target. Drop "target"? > + > +properties: > + compatible: > + items: Will there be anymore? If not, drop items and only have const. > + - const: qcom,sc7280-mdss > + > + reg: > + maxItems: 1 > + > + reg-names: > + const: mdss > + > + power-domains: > + maxItems: 1 > + > + clocks: > + items: > + - description: Display AHB clock from gcc > + - description: Display AHB clock from dispcc > + - description: Display core clock > + > + clock-names: > + items: > + - const: iface > + - const: ahb > + - const: core > + > + interrupts: > + maxItems: 1 > + > + interrupt-controller: true > + > + "#address-cells": true > + > + "#size-cells": true > + > + "#interrupt-cells": > + const: 1 > + > + iommus: > + items: > + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 > + > + ranges: true > + > + interconnects: > + items: > + - description: Interconnect path specifying the port ids for data bus > + > + interconnect-names: > + const: mdp0-mem > + > +patternProperties: > + "^display-controller@[0-9a-f]+$": > + type: object > + description: Node containing the properties of DPU. > + > + properties: > + compatible: > + items: > + - const: qcom,sc7280-dpu Will there be anymore? If not, drop items and only have const. > + > + reg: > + items: > + - description: Address offset and size for mdp register set > + - description: Address offset and size for vbif register set > + > + reg-names: > + items: > + - const: mdp > + - const: vbif > + > + clocks: > + items: > + - description: Display hf axi clock > + - description: Display sf axi clock > + - description: Display ahb clock > + - description: Display lut clock > + - description: Display core clock > + - description: Display vsync clock > + > + clock-names: > + items: > + - const: bus > + - const: nrt_bus > + - const: iface > + - const: lut > + - const: core > + - const: vsync > + > + interrupts: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + operating-points-v2: true > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + description: | > + Contains the list of output ports from DPU device. These ports > + connect to interfaces that are external to the DPU hardware, > + such as DSI, DP etc. Each output port contains an endpoint that > + describes how it is connected to an external interface. > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: DPU_INTF1 (DSI) > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: DPU_INTF5 (EDP) > + > + required: > + - port@0 > + > + required: > + - compatible > + - reg > + - reg-names > + - clocks > + - interrupts > + - power-domains > + - operating-points-v2 > + - ports > + > +required: > + - compatible > + - reg > + - reg-names > + - power-domains > + - clocks > + - interrupts > + - interrupt-controller > + - iommus > + - ranges > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,dispcc-sc7280.h> > + #include <dt-bindings/clock/qcom,gcc-sc7280.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interconnect/qcom,sc7280.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + > + display-subsystem@ae00000 { Maybe just 'subsystem' as that is generic enough. > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "qcom,sc7280-mdss"; > + reg = <0xae00000 0x1000>; > + reg-names = "mdss"; > + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; > + clocks = <&gcc GCC_DISP_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>; > + clock-names = "iface", "ahb", "core"; Can these names be one per line? It makes it easier to match to the clocks property above. > + > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; > + interconnect-names = "mdp0-mem"; > + > + iommus = <&apps_smmu 0x900 0x402>; > + ranges; > + > + display-controller@ae01000 { > + compatible = "qcom,sc7280-dpu"; > + reg = <0x0ae01000 0x8f000>, > + <0x0aeb0000 0x2008>; > + > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", "nrt_bus", "iface", "lut", "core", > + "vsync"; Can these names be one per line? It makes it easier to match to the clocks property above. > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + power-domains = <&rpmhpd SC7280_CX>; > + operating-points-v2 = <&mdp_opp_table>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&dsi0_in>; Tabbed one too many times. > + }; > + }; > + > + port@1 { > + reg = <1>; > + dpu_intf5_out: endpoint { > + remote-endpoint = <&edp_in>; Tabbed one too many times. > + }; > + }; > + }; > + }; > + };
Quoting Krishna Manikandan (2021-08-18 03:27:01) > MSM Mobile Display Subsystem (MDSS) encapsulates sub-blocks > like DPU display controller, DSI, EDP etc. Add required DPU > device tree bindings for SC7280. > > Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org> > --- Please send a cover-letter next time. Do you have the display port dts bits and driver code ready too? Can it be part of this patch series?
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml new file mode 100644 index 0000000..3d256c0 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml @@ -0,0 +1,228 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dpu-sc7280.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU dt properties for SC7280 target + +maintainers: + - Krishna Manikandan <mkrishn@codeaurora.org> + +description: | + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS and DPU are mentioned for SC7280 target. + +properties: + compatible: + items: + - const: qcom,sc7280-mdss + + reg: + maxItems: 1 + + reg-names: + const: mdss + + power-domains: + maxItems: 1 + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AHB clock from dispcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: ahb + - const: core + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#address-cells": true + + "#size-cells": true + + "#interrupt-cells": + const: 1 + + iommus: + items: + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 + + ranges: true + + interconnects: + items: + - description: Interconnect path specifying the port ids for data bus + + interconnect-names: + const: mdp0-mem + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + description: Node containing the properties of DPU. + + properties: + compatible: + items: + - const: qcom,sc7280-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display ahb clock + - description: Display lut clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: bus + - const: nrt_bus + - const: iface + - const: lut + - const: core + - const: vsync + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + operating-points-v2: true + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF1 (DSI) + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF5 (EDP) + + required: + - port@0 + + required: + - compatible + - reg + - reg-names + - clocks + - interrupts + - power-domains + - operating-points-v2 + - ports + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - interrupts + - interrupt-controller + - iommus + - ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sc7280.h> + #include <dt-bindings/clock/qcom,gcc-sc7280.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sc7280.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@ae00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sc7280-mdss"; + reg = <0xae00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "ahb", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; + interconnect-names = "mdp0-mem"; + + iommus = <&apps_smmu 0x900 0x402>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sc7280-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "nrt_bus", "iface", "lut", "core", + "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf5_out: endpoint { + remote-endpoint = <&edp_in>; + }; + }; + }; + }; + }; +...
MSM Mobile Display Subsystem (MDSS) encapsulates sub-blocks like DPU display controller, DSI, EDP etc. Add required DPU device tree bindings for SC7280. Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org> --- .../bindings/display/msm/dpu-sc7280.yaml | 228 +++++++++++++++++++++ 1 file changed, 228 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml