| Message ID | 1629458622-4915-4-git-send-email-okukatla@codeaurora.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add L3 provider support for SC7280 | expand |
Quoting Odelu Kukatla (2021-08-20 04:23:41) > Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 > SoCs. > > Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 53a21d0..cf59b47 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -1848,6 +1848,17 @@ > }; > }; > > + epss_l3: interconnect@18590000 { > + compatible = "qcom,sc7280-epss-l3"; > + reg = <0 0x18590000 0 1000>, Is this supposed to be 0x1000? > + <0 0x18591000 0 0x100>, > + <0 0x18592000 0 0x100>, > + <0 0x18593000 0 0x100>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; > + clock-names = "xo", "alternate"; > + #interconnect-cells = <1>; > + }; > + > cpufreq_hw: cpufreq@18591000 { > compatible = "qcom,cpufreq-epss"; > reg = <0 0x18591100 0 0x900>, > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project >
On 2021-09-04 00:36, Stephen Boyd wrote: > Quoting Odelu Kukatla (2021-08-20 04:23:41) >> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 >> SoCs. >> >> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 11 +++++++++++ >> 1 file changed, 11 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 53a21d0..cf59b47 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -1848,6 +1848,17 @@ >> }; >> }; >> >> + epss_l3: interconnect@18590000 { >> + compatible = "qcom,sc7280-epss-l3"; >> + reg = <0 0x18590000 0 1000>, > > Is this supposed to be 0x1000? > No, This is 1000 or 0x3E8. >> + <0 0x18591000 0 0x100>, >> + <0 0x18592000 0 0x100>, >> + <0 0x18593000 0 0x100>; >> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc >> GCC_GPLL0>; >> + clock-names = "xo", "alternate"; >> + #interconnect-cells = <1>; >> + }; >> + >> cpufreq_hw: cpufreq@18591000 { >> compatible = "qcom,cpufreq-epss"; >> reg = <0 0x18591100 0 0x900>, >> -- >> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora >> Forum, >> a Linux Foundation Collaborative Project >>
On 2021-09-15 10:35, okukatla@codeaurora.org wrote: > On 2021-09-04 00:36, Stephen Boyd wrote: >> Quoting Odelu Kukatla (2021-08-20 04:23:41) >>> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 >>> SoCs. >>> >>> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> >>> --- >>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 11 +++++++++++ >>> 1 file changed, 11 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi >>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi >>> index 53a21d0..cf59b47 100644 >>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >>> @@ -1848,6 +1848,17 @@ >>> }; >>> }; >>> >>> + epss_l3: interconnect@18590000 { >>> + compatible = "qcom,sc7280-epss-l3"; >>> + reg = <0 0x18590000 0 1000>, >> >> Is this supposed to be 0x1000? >> > No, This is 1000 or 0x3E8. We have mapped only required registers for L3 scaling, 1000/0x3E8 is suffice. But i will update it to 0x1000 in next revision so that entire clock domain region-0 is mapped. >>> + <0 0x18591000 0 0x100>, >>> + <0 0x18592000 0 0x100>, >>> + <0 0x18593000 0 0x100>; >>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc >>> GCC_GPLL0>; >>> + clock-names = "xo", "alternate"; >>> + #interconnect-cells = <1>; >>> + }; >>> + >>> cpufreq_hw: cpufreq@18591000 { >>> compatible = "qcom,cpufreq-epss"; >>> reg = <0 0x18591100 0 0x900>, >>> -- >>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora >>> Forum, >>> a Linux Foundation Collaborative Project >>>
Quoting okukatla@codeaurora.org (2021-09-14 23:26:19) > On 2021-09-15 10:35, okukatla@codeaurora.org wrote: > > On 2021-09-04 00:36, Stephen Boyd wrote: > >> Quoting Odelu Kukatla (2021-08-20 04:23:41) > >>> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 > >>> SoCs. > >>> > >>> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> > >>> --- > >>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 11 +++++++++++ > >>> 1 file changed, 11 insertions(+) > >>> > >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi > >>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi > >>> index 53a21d0..cf59b47 100644 > >>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > >>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > >>> @@ -1848,6 +1848,17 @@ > >>> }; > >>> }; > >>> > >>> + epss_l3: interconnect@18590000 { > >>> + compatible = "qcom,sc7280-epss-l3"; > >>> + reg = <0 0x18590000 0 1000>, > >> > >> Is this supposed to be 0x1000? > >> > > No, This is 1000 or 0x3E8. Wow ok. Why is it the only size that isn't in hex format? Please try to be consistent and use hex throughout. > We have mapped only required registers for L3 scaling, 1000/0x3E8 is > suffice. > But i will update it to 0x1000 in next revision so that entire clock > domain region-0 is mapped. Doesn't that conflict with the cpufreq-hw device? > >>> + <0 0x18591000 0 0x100>, > >>> + <0 0x18592000 0 0x100>, > >>> + <0 0x18593000 0 0x100>; > >>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc > >>> GCC_GPLL0>; > >>> + clock-names = "xo", "alternate"; > >>> + #interconnect-cells = <1>; > >>> + }; > >>> + > >>> cpufreq_hw: cpufreq@18591000 { > >>> compatible = "qcom,cpufreq-epss"; > >>> reg = <0 0x18591100 0 0x900>,
On 2021-09-16 01:10, Stephen Boyd wrote: > Quoting okukatla@codeaurora.org (2021-09-14 23:26:19) >> On 2021-09-15 10:35, okukatla@codeaurora.org wrote: >> > On 2021-09-04 00:36, Stephen Boyd wrote: >> >> Quoting Odelu Kukatla (2021-08-20 04:23:41) >> >>> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 >> >>> SoCs. >> >>> >> >>> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> >> >>> --- >> >>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 11 +++++++++++ >> >>> 1 file changed, 11 insertions(+) >> >>> >> >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> >>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> >>> index 53a21d0..cf59b47 100644 >> >>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> >>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> >>> @@ -1848,6 +1848,17 @@ >> >>> }; >> >>> }; >> >>> >> >>> + epss_l3: interconnect@18590000 { >> >>> + compatible = "qcom,sc7280-epss-l3"; >> >>> + reg = <0 0x18590000 0 1000>, >> >> >> >> Is this supposed to be 0x1000? >> >> >> > No, This is 1000 or 0x3E8. > > Wow ok. Why is it the only size that isn't in hex format? Please try to > be consistent and use hex throughout. > Sure, will update it to hex format in new revision. >> We have mapped only required registers for L3 scaling, 1000/0x3E8 is >> suffice. >> But i will update it to 0x1000 in next revision so that entire clock >> domain region-0 is mapped. > > Doesn't that conflict with the cpufreq-hw device? > epss_l3 maps (0x18590000, size:0x1000) region which cpufreq-hw does not need. I will update size to 0x1000 for this region only. >> >>> + <0 0x18591000 0 0x100>, >> >>> + <0 0x18592000 0 0x100>, >> >>> + <0 0x18593000 0 0x100>; >> >>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc >> >>> GCC_GPLL0>; >> >>> + clock-names = "xo", "alternate"; >> >>> + #interconnect-cells = <1>; >> >>> + }; >> >>> + >> >>> cpufreq_hw: cpufreq@18591000 { >> >>> compatible = "qcom,cpufreq-epss"; >> >>> reg = <0 0x18591100 0 0x900>,
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 53a21d0..cf59b47 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1848,6 +1848,17 @@ }; }; + epss_l3: interconnect@18590000 { + compatible = "qcom,sc7280-epss-l3"; + reg = <0 0x18590000 0 1000>, + <0 0x18591000 0 0x100>, + <0 0x18592000 0 0x100>, + <0 0x18593000 0 0x100>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18591000 { compatible = "qcom,cpufreq-epss"; reg = <0 0x18591100 0 0x900>,
Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 SoCs. Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)