| Message ID | 1635250764-13994-3-git-send-email-srivasam@codeaurora.org (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | Update SoundWire RX and TX cgcr register control | expand |
On Tue, 26 Oct 2021 17:49:23 +0530, Srinivasa Rao Mandadapu wrote: > Update description for RX and TX cgcr register control property required for > soundwire version 1.6.0 and above. > > Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> > Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org> > Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org> > --- > Documentation/devicetree/bindings/soundwire/qcom,sdw.txt | 9 +++++++++ > 1 file changed, 9 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
Quoting Srinivasa Rao Mandadapu (2021-10-26 05:19:23) > Update description for RX and TX cgcr register control property required for > soundwire version 1.6.0 and above. > > Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> > Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org> > Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org> > --- > Documentation/devicetree/bindings/soundwire/qcom,sdw.txt | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt b/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt > index b93a2b3..91b9086 100644 > --- a/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt > +++ b/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt > @@ -150,6 +150,15 @@ board specific bus parameters. > or applicable for the respective data port. > More info in MIPI Alliance SoundWire 1.0 Specifications. > > +- qcom,swrm-hctl-reg: > + Usage: optional > + Value type: <prop-encoded-array> > + Definition: The base address of SoundWire RX and TX cgcr register > + address space. cgcr is "clock gate control register"? > + This is to update soundwire master rxtx cgcr register field to > + make clock gating control as software controllable for RX path and > + TX path which is required for SoundWire version 1.6.0 and above. Nak. Use clk APIs to control clks, not direct MMIO writes into a different device.
diff --git a/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt b/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt index b93a2b3..91b9086 100644 --- a/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt +++ b/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt @@ -150,6 +150,15 @@ board specific bus parameters. or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. +- qcom,swrm-hctl-reg: + Usage: optional + Value type: <prop-encoded-array> + Definition: The base address of SoundWire RX and TX cgcr register + address space. + This is to update soundwire master rxtx cgcr register field to + make clock gating control as software controllable for RX path and + TX path which is required for SoundWire version 1.6.0 and above. + Note: More Information on detail of encoding of these fields can be found in MIPI Alliance SoundWire 1.0 Specifications.