| Message ID | 1637060508-30375-4-git-send-email-pmaliset@codeaurora.org (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | Add PCIe clock DT entries for SC7280 | expand |
Quoting Prasad Malisetty (2021-11-16 03:01:48) > Update interrupt-map parent address cells for sc7280 > Similar to existing Qcom SoCs. > > Fixes: 92e0ee9f8 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes") > There shouldn't be a newline between Fixes and SoB > Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 3fb9338..9ca9c31 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1593,10 +1593,10 @@ interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
Update interrupt-map parent address cells for sc7280 Similar to existing Qcom SoCs. Fixes: 92e0ee9f8 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes") Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org> --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)