| Message ID | 1642586079-12472-1-git-send-email-loic.poulain@linaro.org (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | drm/msm/dsi: Fix byte clock interface rate for 14nm PHY | expand |
On Wed, 19 Jan 2022 at 12:42, Loic Poulain <loic.poulain@linaro.org> wrote: > > According to downstream driver, byte intf clk rate should be half the > byte clk only with DSI PHY verion above 2.0 (14nm): > https://source.codeaurora.org/quic/la/platform/vendor/opensource/display-drivers/tree/msm/dsi/dsi_display.c?h=LA.UM.8.12.3.1#n3991 This is a bit strange. We have other 14nm DSI PHYs, which are thought to be working (msm8996, sdm660). Not tested by me, though. And msm8916 has 28nm-lp, which according to CAF's patch should also use > > This change introduces a no_byte_intf_clk_div phy property, used to > control byte clk intf divider. > > This fixes DSI sync issues on 14nm based DSI Phy platorms. > > Tested with: > - QCM2290 (14nm phy) + tc358767 DSI/DPI bridge > - QCM2290 (14nm phy) + lontium lt9611uxc DSI/HDMI bridge > > Signed-off-by: Loic Poulain <loic.poulain@linaro.org> > --- > drivers/gpu/drm/msm/dsi/dsi_host.c | 5 ++++- > drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + > drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 3 +++ > 3 files changed, 8 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c > index 428641e..1f8287a 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi_host.c > +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c > @@ -172,6 +172,8 @@ struct msm_dsi_host { > /* from phy DT */ > bool cphy_mode; > > + bool phy_no_byte_intf_clk_div; > + Ugh. I'd suggest adding this kind of field to msm_dsi_phy_shared_timings and then passing shared timings to link_clk_set_rate callback. > u32 dma_cmd_ctrl_restore; > > bool registered; > @@ -484,7 +486,7 @@ int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) > > if (msm_host->byte_intf_clk) { > /* For CPHY, byte_intf_clk is same as byte_clk */ > - if (msm_host->cphy_mode) > + if (msm_host->cphy_mode || msm_host->phy_no_byte_intf_clk_div) > byte_intf_rate = msm_host->byte_clk_rate; > else > byte_intf_rate = msm_host->byte_clk_rate / 2; > @@ -2196,6 +2198,7 @@ int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, Note there is no msm_dsi_host_set_src_pll() anymore. Could you please rebase on top of msm-next? > int ret; > > msm_host->cphy_mode = src_phy->cphy_mode; > + msm_host->phy_no_byte_intf_clk_div = src_phy->no_byte_intf_clk_div; > > ret = msm_dsi_phy_get_clk_provider(src_phy, > &byte_clk_provider, &pixel_clk_provider); > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > index 4c82575..06d2284 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > @@ -103,6 +103,7 @@ struct msm_dsi_phy { > enum msm_dsi_phy_usecase usecase; > bool regulator_ldo_mode; > bool cphy_mode; > + bool no_byte_intf_clk_div; > > struct clk_hw *vco_hw; > bool pll_on; > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > index 7414966..f4849e6 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > @@ -897,6 +897,9 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) > > phy->vco_hw = &pll_14nm->clk_hw; > > + /* For PHY version <= 2.0 (14nm), byte_intf_clk = byte_clk */ > + phy->no_byte_intf_clk_div = true; This setting can go into constant phy configuration instead. And also note that there are other <= 2.0 PHYs (20nm, 28nm). Do they share this property?
Hi Dm On Wed, 19 Jan 2022 at 11:45, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote: > > On Wed, 19 Jan 2022 at 12:42, Loic Poulain <loic.poulain@linaro.org> wrote: > > > > According to downstream driver, byte intf clk rate should be half the > > byte clk only with DSI PHY verion above 2.0 (14nm): > > https://source.codeaurora.org/quic/la/platform/vendor/opensource/display-drivers/tree/msm/dsi/dsi_display.c?h=LA.UM.8.12.3.1#n3991 > > This is a bit strange. We have other 14nm DSI PHYs, which are thought > to be working (msm8996, sdm660). Not tested by me, though. > And msm8916 has 28nm-lp, which according to CAF's patch should also use Yes, It's not clear to me if this clock configuration is just a recommendation or a requirement. All I can say is that it fixes DSI issue on QCM2290 14nm, so maybe I should be more conservative and restrict this behaviour to QCM2290 phy only? [...] > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > > index 7414966..f4849e6 100644 > > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > > @@ -897,6 +897,9 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) > > > > phy->vco_hw = &pll_14nm->clk_hw; > > > > + /* For PHY version <= 2.0 (14nm), byte_intf_clk = byte_clk */ > > + phy->no_byte_intf_clk_div = true; > > This setting can go into constant phy configuration instead. And also > note that there are other <= 2.0 PHYs (20nm, 28nm). > Do they share this property? According to downstream, yes, but I can not test on other PHYs. Regards, Loic
On 19.01.2022 10:54, Loic Poulain wrote: > According to downstream driver, byte intf clk rate should be half the > byte clk only with DSI PHY verion above 2.0 (14nm): > https://source.codeaurora.org/quic/la/platform/vendor/opensource/display-drivers/tree/msm/dsi/dsi_display.c?h=LA.UM.8.12.3.1#n3991 > > This change introduces a no_byte_intf_clk_div phy property, used to > control byte clk intf divider. > > This fixes DSI sync issues on 14nm based DSI Phy platorms. > > Tested with: > - QCM2290 (14nm phy) + tc358767 DSI/DPI bridge > - QCM2290 (14nm phy) + lontium lt9611uxc DSI/HDMI bridge > > Signed-off-by: Loic Poulain <loic.poulain@linaro.org> > --- Required for the DSI display to function on SM6115 Lenovo Tab P11 Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > drivers/gpu/drm/msm/dsi/dsi_host.c | 5 ++++- > drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + > drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 3 +++ > 3 files changed, 8 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c > index 428641e..1f8287a 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi_host.c > +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c > @@ -172,6 +172,8 @@ struct msm_dsi_host { > /* from phy DT */ > bool cphy_mode; > > + bool phy_no_byte_intf_clk_div; > + > u32 dma_cmd_ctrl_restore; > > bool registered; > @@ -484,7 +486,7 @@ int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) > > if (msm_host->byte_intf_clk) { > /* For CPHY, byte_intf_clk is same as byte_clk */ > - if (msm_host->cphy_mode) > + if (msm_host->cphy_mode || msm_host->phy_no_byte_intf_clk_div) > byte_intf_rate = msm_host->byte_clk_rate; > else > byte_intf_rate = msm_host->byte_clk_rate / 2; > @@ -2196,6 +2198,7 @@ int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, > int ret; > > msm_host->cphy_mode = src_phy->cphy_mode; > + msm_host->phy_no_byte_intf_clk_div = src_phy->no_byte_intf_clk_div; > > ret = msm_dsi_phy_get_clk_provider(src_phy, > &byte_clk_provider, &pixel_clk_provider); > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > index 4c82575..06d2284 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > @@ -103,6 +103,7 @@ struct msm_dsi_phy { > enum msm_dsi_phy_usecase usecase; > bool regulator_ldo_mode; > bool cphy_mode; > + bool no_byte_intf_clk_div; > > struct clk_hw *vco_hw; > bool pll_on; > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > index 7414966..f4849e6 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > @@ -897,6 +897,9 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) > > phy->vco_hw = &pll_14nm->clk_hw; > > + /* For PHY version <= 2.0 (14nm), byte_intf_clk = byte_clk */ > + phy->no_byte_intf_clk_div = true; > + > return 0; > } > >
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 428641e..1f8287a 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -172,6 +172,8 @@ struct msm_dsi_host { /* from phy DT */ bool cphy_mode; + bool phy_no_byte_intf_clk_div; + u32 dma_cmd_ctrl_restore; bool registered; @@ -484,7 +486,7 @@ int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) if (msm_host->byte_intf_clk) { /* For CPHY, byte_intf_clk is same as byte_clk */ - if (msm_host->cphy_mode) + if (msm_host->cphy_mode || msm_host->phy_no_byte_intf_clk_div) byte_intf_rate = msm_host->byte_clk_rate; else byte_intf_rate = msm_host->byte_clk_rate / 2; @@ -2196,6 +2198,7 @@ int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, int ret; msm_host->cphy_mode = src_phy->cphy_mode; + msm_host->phy_no_byte_intf_clk_div = src_phy->no_byte_intf_clk_div; ret = msm_dsi_phy_get_clk_provider(src_phy, &byte_clk_provider, &pixel_clk_provider); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 4c82575..06d2284 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -103,6 +103,7 @@ struct msm_dsi_phy { enum msm_dsi_phy_usecase usecase; bool regulator_ldo_mode; bool cphy_mode; + bool no_byte_intf_clk_div; struct clk_hw *vco_hw; bool pll_on; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 7414966..f4849e6 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -897,6 +897,9 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) phy->vco_hw = &pll_14nm->clk_hw; + /* For PHY version <= 2.0 (14nm), byte_intf_clk = byte_clk */ + phy->no_byte_intf_clk_div = true; + return 0; }
According to downstream driver, byte intf clk rate should be half the byte clk only with DSI PHY verion above 2.0 (14nm): https://source.codeaurora.org/quic/la/platform/vendor/opensource/display-drivers/tree/msm/dsi/dsi_display.c?h=LA.UM.8.12.3.1#n3991 This change introduces a no_byte_intf_clk_div phy property, used to control byte clk intf divider. This fixes DSI sync issues on 14nm based DSI Phy platorms. Tested with: - QCM2290 (14nm phy) + tc358767 DSI/DPI bridge - QCM2290 (14nm phy) + lontium lt9611uxc DSI/HDMI bridge Signed-off-by: Loic Poulain <loic.poulain@linaro.org> --- drivers/gpu/drm/msm/dsi/dsi_host.c | 5 ++++- drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 3 +++ 3 files changed, 8 insertions(+), 1 deletion(-)