| Message ID | 1644334454-16719-2-git-send-email-quic_srivasam@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add lpass pin control support for audio on sc7280 based targets | expand |
Quoting Srinivasa Rao Mandadapu (2022-02-08 07:34:12) > Add AMP enable node and pinmux for primary and secondary I2S > for SC7280 based platforms. > > Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> > Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> > Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 40 ++++++++++++++++++++++++++++++++ > arch/arm64/boot/dts/qcom/sc7280.dtsi | 40 ++++++++++++++++++++++++++++++++ > 2 files changed, 80 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi > index d623d71..c7d6c46 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi > @@ -436,6 +436,39 @@ > qcom,drive-strength = <3>; > }; > }; Newline here > +&pri_mi2s_data0 { > + drive-strength = <6>; > +}; > + > +&pri_mi2s_data1 { > + drive-strength = <6>; > +}; > + > +&pri_mi2s_mclk { > + drive-strength = <6>; > +}; > + > +&pri_mi2s_sclk { > + drive-strength = <6>; > +}; > + > +&pri_mi2s_ws { > + drive-strength = <6>; > +}; > + > +&sec_mi2s_data0 { > + drive-strength = <6>; > + bias-disable; > +}; > + > +&sec_mi2s_sclk { > + drive-strength = <6>; > + bias-disable; > +}; > + > +&sec_mi2s_ws { > + drive-strength = <6>; > +}; Please sort these nodes alphabetically on node name. > > &qspi_cs0 { > bias-disable; > @@ -491,6 +524,13 @@ > }; > > &tlmm { > + amp_en: amp-en { > + pins = "gpio63"; > + function = "gpio"; > + bias-disable; Is there an external pull? > + drive-strength = <2>; > + }; > + > nvme_pwren: nvme-pwren { > function = "gpio"; > }; > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 937c2e0..76e73e9 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -3461,6 +3461,46 @@ > }; > }; > > + pri_mi2s_data0: pri-mi2s-data0 { > + pins = "gpio98"; > + function = "mi2s0_data0"; > + }; > + > + pri_mi2s_data1: pri-mi2s-data1 { > + pins = "gpio99"; > + function = "mi2s0_data1"; > + }; > + > + pri_mi2s_mclk: pri-mi2s-mclk { > + pins = "gpio96"; > + function = "pri_mi2s"; > + }; > + > + pri_mi2s_sclk: pri-mi2s-sclk { > + pins = "gpio97"; > + function = "mi2s0_sck"; > + }; > + > + pri_mi2s_ws: pri-mi2s-ws { > + pins = "gpio100"; > + function = "mi2s0_ws"; > + }; > + > + sec_mi2s_data0: sec-mi2s-data0 { > + pins = "gpio107"; > + function = "mi2s1_data0"; > + }; > + > + sec_mi2s_sclk: sec-mi2s-sclk { > + pins = "gpio106"; > + function = "mi2s1_sck"; > + }; > + > + sec_mi2s_ws: sec-mi2s-ws { > + pins = "gpio108"; > + function = "mi2s1_ws"; > + }; Please sort these nodes alphabetically on node name.
On 2/9/2022 2:38 AM, Stephen Boyd wrote: Thanks for your time Stephen!!! > Quoting Srinivasa Rao Mandadapu (2022-02-08 07:34:12) >> Add AMP enable node and pinmux for primary and secondary I2S >> for SC7280 based platforms. >> >> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> >> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> >> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 40 ++++++++++++++++++++++++++++++++ >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 40 ++++++++++++++++++++++++++++++++ >> 2 files changed, 80 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi >> index d623d71..c7d6c46 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi >> @@ -436,6 +436,39 @@ >> qcom,drive-strength = <3>; >> }; >> }; > Newline here Okay. will remove it. > >> +&pri_mi2s_data0 { >> + drive-strength = <6>; >> +}; >> + >> +&pri_mi2s_data1 { >> + drive-strength = <6>; >> +}; >> + >> +&pri_mi2s_mclk { >> + drive-strength = <6>; >> +}; >> + >> +&pri_mi2s_sclk { >> + drive-strength = <6>; >> +}; >> + >> +&pri_mi2s_ws { >> + drive-strength = <6>; >> +}; >> + >> +&sec_mi2s_data0 { >> + drive-strength = <6>; >> + bias-disable; >> +}; >> + >> +&sec_mi2s_sclk { >> + drive-strength = <6>; >> + bias-disable; >> +}; >> + >> +&sec_mi2s_ws { >> + drive-strength = <6>; >> +}; > Please sort these nodes alphabetically on node name. Okay. > >> &qspi_cs0 { >> bias-disable; >> @@ -491,6 +524,13 @@ >> }; >> >> &tlmm { >> + amp_en: amp-en { >> + pins = "gpio63"; >> + function = "gpio"; >> + bias-disable; > Is there an external pull? I think no external pull. In trogdor mentioned bias-pull-down but you suggested to remove it. > >> + drive-strength = <2>; >> + }; >> + >> nvme_pwren: nvme-pwren { >> function = "gpio"; >> }; >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 937c2e0..76e73e9 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -3461,6 +3461,46 @@ >> }; >> }; >> >> + pri_mi2s_data0: pri-mi2s-data0 { >> + pins = "gpio98"; >> + function = "mi2s0_data0"; >> + }; >> + >> + pri_mi2s_data1: pri-mi2s-data1 { >> + pins = "gpio99"; >> + function = "mi2s0_data1"; >> + }; >> + >> + pri_mi2s_mclk: pri-mi2s-mclk { >> + pins = "gpio96"; >> + function = "pri_mi2s"; >> + }; >> + >> + pri_mi2s_sclk: pri-mi2s-sclk { >> + pins = "gpio97"; >> + function = "mi2s0_sck"; >> + }; >> + >> + pri_mi2s_ws: pri-mi2s-ws { >> + pins = "gpio100"; >> + function = "mi2s0_ws"; >> + }; >> + >> + sec_mi2s_data0: sec-mi2s-data0 { >> + pins = "gpio107"; >> + function = "mi2s1_data0"; >> + }; >> + >> + sec_mi2s_sclk: sec-mi2s-sclk { >> + pins = "gpio106"; >> + function = "mi2s1_sck"; >> + }; >> + >> + sec_mi2s_ws: sec-mi2s-ws { >> + pins = "gpio108"; >> + function = "mi2s1_ws"; >> + }; > Please sort these nodes alphabetically on node name. Okay.
Quoting Srinivasa Rao Mandadapu (2022-02-09 05:42:40) > > On 2/9/2022 2:38 AM, Stephen Boyd wrote: > > Quoting Srinivasa Rao Mandadapu (2022-02-08 07:34:12) > >> &qspi_cs0 { > >> bias-disable; > >> @@ -491,6 +524,13 @@ > >> }; > >> > >> &tlmm { > >> + amp_en: amp-en { > >> + pins = "gpio63"; > >> + function = "gpio"; > >> + bias-disable; > > Is there an external pull? > I think no external pull. In trogdor mentioned bias-pull-down but you > suggested to remove it. Maybe on trogdor there was an external pull inside the amp that this pin is connected to? Usually we have a comment like /* Has external pull-{up,down} */ so please add that here depending on which way the pull goes.
On 2/10/2022 5:37 AM, Stephen Boyd wrote: Thanks for Your time Stephen!!! > Quoting Srinivasa Rao Mandadapu (2022-02-09 05:42:40) >> On 2/9/2022 2:38 AM, Stephen Boyd wrote: >>> Quoting Srinivasa Rao Mandadapu (2022-02-08 07:34:12) >>>> &qspi_cs0 { >>>> bias-disable; >>>> @@ -491,6 +524,13 @@ >>>> }; >>>> >>>> &tlmm { >>>> + amp_en: amp-en { >>>> + pins = "gpio63"; >>>> + function = "gpio"; >>>> + bias-disable; >>> Is there an external pull? >> I think no external pull. In trogdor mentioned bias-pull-down but you >> suggested to remove it. > Maybe on trogdor there was an external pull inside the amp that this pin > is connected to? Usually we have a comment like /* Has external > pull-{up,down} */ so please add that here depending on which way the > pull goes. As per Anderson suggestion we removed bias-pull-down. Actually, it's up-streamed for same platform in sc7280-herobrine.dtsi. We will fallow the same. It contains bias-pull-down.
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index d623d71..c7d6c46 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -436,6 +436,39 @@ qcom,drive-strength = <3>; }; }; +&pri_mi2s_data0 { + drive-strength = <6>; +}; + +&pri_mi2s_data1 { + drive-strength = <6>; +}; + +&pri_mi2s_mclk { + drive-strength = <6>; +}; + +&pri_mi2s_sclk { + drive-strength = <6>; +}; + +&pri_mi2s_ws { + drive-strength = <6>; +}; + +&sec_mi2s_data0 { + drive-strength = <6>; + bias-disable; +}; + +&sec_mi2s_sclk { + drive-strength = <6>; + bias-disable; +}; + +&sec_mi2s_ws { + drive-strength = <6>; +}; &qspi_cs0 { bias-disable; @@ -491,6 +524,13 @@ }; &tlmm { + amp_en: amp-en { + pins = "gpio63"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + nvme_pwren: nvme-pwren { function = "gpio"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 937c2e0..76e73e9 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3461,6 +3461,46 @@ }; }; + pri_mi2s_data0: pri-mi2s-data0 { + pins = "gpio98"; + function = "mi2s0_data0"; + }; + + pri_mi2s_data1: pri-mi2s-data1 { + pins = "gpio99"; + function = "mi2s0_data1"; + }; + + pri_mi2s_mclk: pri-mi2s-mclk { + pins = "gpio96"; + function = "pri_mi2s"; + }; + + pri_mi2s_sclk: pri-mi2s-sclk { + pins = "gpio97"; + function = "mi2s0_sck"; + }; + + pri_mi2s_ws: pri-mi2s-ws { + pins = "gpio100"; + function = "mi2s0_ws"; + }; + + sec_mi2s_data0: sec-mi2s-data0 { + pins = "gpio107"; + function = "mi2s1_data0"; + }; + + sec_mi2s_sclk: sec-mi2s-sclk { + pins = "gpio106"; + function = "mi2s1_sck"; + }; + + sec_mi2s_ws: sec-mi2s-ws { + pins = "gpio108"; + function = "mi2s1_ws"; + }; + qup_uart8_cts: qup-uart8-cts { pins = "gpio32"; function = "qup10";