From patchwork Mon Feb 14 07:02:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12745039 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B3A4C433F5 for ; Mon, 14 Feb 2022 07:02:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232100AbiBNHCa (ORCPT ); Mon, 14 Feb 2022 02:02:30 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:55976 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241113AbiBNHC3 (ORCPT ); Mon, 14 Feb 2022 02:02:29 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F16F6580D8; Sun, 13 Feb 2022 23:02:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644822143; x=1676358143; h=from:to:cc:subject:date:message-id; bh=dO5l/En4m8ZREkWl9lrDIcLcLCuIjcDgtaL8yi+zZeg=; b=eVQVAjupypQxjgHy394w0qoHkHMXTrH7WmgLhqwpusLyn2qtGCc403io 48cytK9Iy8fTKYRBFYJlSAN14QAE7v549avk7EcyYFXTP5qR28j8FTHof mE8JS/O+sB93efDyXdH278m0GUi8gU3BY724Pb8MmzLIkkRqJvcBI1N3H w=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 13 Feb 2022 23:02:23 -0800 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; 13 Feb 2022 23:02:21 -0800 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg01-blr.qualcomm.com with ESMTP; 14 Feb 2022 12:32:19 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 31F544473; Mon, 14 Feb 2022 12:32:18 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH 6/8] ARM: dts: qcom: sdx65: Add support for APCS block Date: Mon, 14 Feb 2022 12:32:17 +0530 Message-Id: <1644822137-27760-1-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The APCS block on SDX65 acts as a mailbox controller and also provides clock output for the Cortex A7 CPU. Signed-off-by: Rohit Agarwal Reviewed-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx65.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 2900ffe..1646c7c 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -133,6 +133,15 @@ #clock-cells = <0>; }; + apcs: mailbox@17810000 { + compatible = "qcom,sdx65-apcs-gcc", "syscon"; + reg = <0x17810000 0x2000>; + #mbox-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; + clock-names = "ref", "pll", "aux"; + #clock-cells = <0>; + }; + timer@17820000 { #address-cells = <1>; #size-cells = <1>;