diff mbox series

[2/3] phy: qcom-snps: Add support for overriding phy tuning parameters

Message ID 1644952755-15527-3-git-send-email-quic_c_sanm@quicinc.com (mailing list archive)
State Superseded
Headers show
Series Add QCOM SNPS PHY overriding params support | expand

Commit Message

Sandeep Maheswaram Feb. 15, 2022, 7:19 p.m. UTC 
Added support for overriding x0,x1,x2,x3 params for SNPS PHY.

Signed-off-by: Sandeep Maheswaram <quic_c_sanm@quicinc.com>
---
 drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 45 +++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)
diff mbox series

Patch

diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
index 7e61202..3cf90fa 100644
--- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
+++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
@@ -51,6 +51,12 @@ 
 #define USB2_SUSPEND_N				BIT(2)
 #define USB2_SUSPEND_N_SEL			BIT(3)
 
+#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X0		(0x6c)
+#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1		(0x70)
+#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2		(0x74)
+#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X3		(0x78)
+#define PARAM_OVRD_MASK			0xFF
+
 #define USB2_PHY_USB_PHY_CFG0			(0x94)
 #define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN	BIT(0)
 #define UTMI_PHY_CMN_CTRL_OVERRIDE_EN		BIT(1)
@@ -90,6 +96,11 @@  struct qcom_snps_hsphy {
 
 	bool phy_initialized;
 	enum phy_mode mode;
+
+	u8 override_x0;
+	u8 override_x1;
+	u8 override_x2;
+	u8 override_x3;
 };
 
 static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset,
@@ -222,6 +233,19 @@  static int qcom_snps_hsphy_init(struct phy *phy)
 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1,
 					VBUSVLDEXT0, VBUSVLDEXT0);
 
+	if (hsphy->override_x0)
+		qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X0,
+					PARAM_OVRD_MASK, hsphy->override_x0);
+	if (hsphy->override_x1)
+		qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1,
+					PARAM_OVRD_MASK, hsphy->override_x1);
+	if (hsphy->override_x2)
+		qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2,
+					PARAM_OVRD_MASK, hsphy->override_x2);
+	if (hsphy->override_x3)
+		qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X3,
+					PARAM_OVRD_MASK, hsphy->override_x3);
+
 	qcom_snps_hsphy_write_mask(hsphy->base,
 					USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2,
 					VREGBYPASS, VREGBYPASS);
@@ -294,6 +318,7 @@  static int qcom_snps_hsphy_probe(struct platform_device *pdev)
 	struct phy *generic_phy;
 	int ret, i;
 	int num;
+	u32 value;
 
 	hsphy = devm_kzalloc(dev, sizeof(*hsphy), GFP_KERNEL);
 	if (!hsphy)
@@ -329,6 +354,26 @@  static int qcom_snps_hsphy_probe(struct platform_device *pdev)
 		return ret;
 	}
 
+	if (!of_property_read_u32(dev->of_node, "qcom,override_x0",
+				  &value)) {
+		hsphy->override_x0 = (u8)value;
+	}
+
+	if (!of_property_read_u32(dev->of_node, "qcom,override_x1",
+				  &value)) {
+		hsphy->override_x1 = (u8)value;
+	}
+
+	if (!of_property_read_u32(dev->of_node, "qcom,override_x2",
+				  &value)) {
+		hsphy->override_x2  = (u8)value;
+	}
+
+	if (!of_property_read_u32(dev->of_node, "qcom,override_x3",
+				  &value)) {
+		hsphy->override_x3 = (u8)value;
+	}
+
 	pm_runtime_set_active(dev);
 	pm_runtime_enable(dev);
 	/*