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[v3,3/7] dt-bindings: clock: Add A7 PLL binding for SDX65

Message ID 1645420953-21176-4-git-send-email-quic_rohiagar@quicinc.com (mailing list archive)
State Superseded
Headers show
Series Add APCS support for SDX65 | expand

Commit Message

Rohit Agarwal Feb. 21, 2022, 5:22 a.m. UTC 
Add YAML binding for Cortex A7 PLL clock in Qualcomm
platforms like SDX65.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
 Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
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Patch

diff --git a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
index 8666e99..b8889dc 100644
--- a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
@@ -10,13 +10,14 @@  maintainers:
   - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
 
 description:
-  The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high
+  The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
   frequency clock to the CPU.
 
 properties:
   compatible:
     enum:
       - qcom,sdx55-a7pll
+      - qcom,sdx65-a7pll
 
   reg:
     maxItems: 1