From patchwork Tue Feb 22 04:56:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12754540 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD056C43217 for ; Tue, 22 Feb 2022 05:37:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229710AbiBVFhe (ORCPT ); Tue, 22 Feb 2022 00:37:34 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:48478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229663AbiBVFhT (ORCPT ); Tue, 22 Feb 2022 00:37:19 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 812F39FCE; Mon, 21 Feb 2022 21:36:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1645508214; x=1677044214; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=uWSnm1hq6utkHH6m0I4spcTX9ZDwfkP1gD4Ehx9LFQE=; b=ImdSiI3vAvL7pOgl9BD6aaNW8i35WhY/GgWgItu2qPwYCKe2OhXTQdd4 cgmsRa7SHF23khgiL/iaYzRwmpYESYSNPbaaK25acpoSwPPm7Zp7UHpZC RHuwVi7k7eG5bsDkREg9Le0d12Iwl0Lw2tHkODbYDSPmkrgaIQIFZAAGe s=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 21 Feb 2022 20:56:49 -0800 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 21 Feb 2022 20:56:47 -0800 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg01-blr.qualcomm.com with ESMTP; 22 Feb 2022 10:26:30 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id E29BB46D6; Tue, 22 Feb 2022 10:26:29 +0530 (+0530) From: Rohit Agarwal To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH v4 3/5] ARM: dts: qcom: sdx65: Add support for A7 PLL clock Date: Tue, 22 Feb 2022 10:26:23 +0530 Message-Id: <1645505785-2271-4-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1645505785-2271-1-git-send-email-quic_rohiagar@quicinc.com> References: <1645505785-2271-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On SDX65 there is a separate A7 PLL which is used to provide high frequency clock to the Cortex A7 CPU via a MUX. Signed-off-by: Rohit Agarwal Reviewed-by: Stephen Boyd Reviewed-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx65.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 653df15..ec80266 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -125,6 +125,14 @@ <0x17802000 0x1000>; }; + a7pll: clock@17808000 { + compatible = "qcom,sdx55-a7pll"; + reg = <0x17808000 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <0>; + }; + timer@17820000 { #address-cells = <1>; #size-cells = <1>;