| Message ID | 1647269217-14064-5-git-send-email-quic_vpolimer@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Update mdp clk to max supported value to support higher refresh rates | expand |
Hi, On Mon, Mar 14, 2022 at 7:47 AM Vinod Polimera <quic_vpolimer@quicinc.com> wrote: > > Drop the assigned clock rate property and vote on the mdp clock as per > calculated value during the usecase. > > This patch is dependent on below patch > https://patchwork.kernel.org/patch/12774067/ > > Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> > Reviewed-by: Stephen Boyd <swboyd@chromium.org> > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 ++------- > 1 file changed, 2 insertions(+), 7 deletions(-) Similar comments to patch #2 about the commit message, but otherwise: Reviewed-by: Douglas Anderson <dianders@chromium.org>
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 41f4e46..c0771d2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4240,9 +4240,6 @@ <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "core"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; @@ -4273,10 +4270,8 @@ <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <300000000>, - <19200000>; + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SDM845_CX>;