From patchwork Thu Mar 17 06:12:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12783575 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78AFBC433F5 for ; Thu, 17 Mar 2022 06:21:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230110AbiCQGXH (ORCPT ); Thu, 17 Mar 2022 02:23:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229713AbiCQGWl (ORCPT ); Thu, 17 Mar 2022 02:22:41 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C117FCF4AC; Wed, 16 Mar 2022 23:12:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647497574; x=1679033574; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=vFm/1iPltzV2y4DMijEhe5IyJTZ/LWY1V45aTZ9IiEs=; b=aQcM4w8+4W9fCZi4c+uNp+vdYori5WDUzAiOoT6iVPtwQ+I3MNa7M2OV tMF4MM0RbMjsNIWxP+qqjjjKNmxiPqkGJencPz11y/njKOHAGnf3L8oQh XcY6nm3i6oABkHn7N9UJh7o4b1Fj+goX26H7j4+j6KvycfEWRp2JMWVLk g=; Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-01.qualcomm.com with ESMTP; 16 Mar 2022 23:12:54 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg03-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2022 23:12:54 -0700 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 23:12:53 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 23:12:51 -0700 From: Fenglin Wu To: , , CC: , , , , , "Ashay Jaiswal" Subject: [PATCH v6 05/10] spmi: pmic-arb: add support to dispatch interrupt based on IRQ status Date: Thu, 17 Mar 2022 14:12:10 +0800 Message-ID: <1647497535-32151-6-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647497535-32151-1-git-send-email-quic_fenglinw@quicinc.com> References: <1647497535-32151-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Ashay Jaiswal Current implementation of SPMI arbiter dispatches interrupt based on the Arbiter's accumulator status, in some cases the accumulator status may remain zero and the interrupt remains un-handled. Add logic to dispatch interrupts based Arbiter's IRQ status if the accumulator status is zero. Signed-off-by: Ashay Jaiswal Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index e19eaec..56f2294 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -630,12 +630,18 @@ static void pmic_arb_chained_irq(struct irq_desc *desc) u8 ee = pmic_arb->ee; u32 status, enable, handled = 0; int i, id, apid; + /* status based dispatch */ + bool acc_valid = false; + u32 irq_status = 0; chained_irq_enter(chip, desc); for (i = first >> 5; i <= last >> 5; ++i) { status = readl_relaxed( ver_ops->owner_acc_status(pmic_arb, ee, i)); + if (status) + acc_valid = true; + while (status) { id = ffs(status) - 1; status &= ~BIT(id); @@ -653,6 +659,29 @@ static void pmic_arb_chained_irq(struct irq_desc *desc) } } + /* ACC_STATUS is empty but IRQ fired check IRQ_STATUS */ + if (!acc_valid) { + for (i = first; i <= last; i++) { + /* skip if APPS is not irq owner */ + if (pmic_arb->apid_data[i].irq_ee != pmic_arb->ee) + continue; + + irq_status = readl_relaxed( + ver_ops->irq_status(pmic_arb, i)); + if (irq_status) { + enable = readl_relaxed( + ver_ops->acc_enable(pmic_arb, i)); + if (enable & SPMI_PIC_ACC_ENABLE_BIT) { + dev_dbg(&pmic_arb->spmic->dev, + "Dispatching IRQ for apid=%d status=%x\n", + i, irq_status); + if (periph_interrupt(pmic_arb, i) != 0) + handled++; + } + } + } + } + if (handled == 0) handle_bad_irq(desc);