From patchwork Wed Apr 13 15:21:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivasa Rao Mandadapu X-Patchwork-Id: 12812127 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30459C433EF for ; Wed, 13 Apr 2022 15:21:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235300AbiDMPYL (ORCPT ); Wed, 13 Apr 2022 11:24:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232655AbiDMPYJ (ORCPT ); Wed, 13 Apr 2022 11:24:09 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C0B2647566; Wed, 13 Apr 2022 08:21:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649863307; x=1681399307; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=gBPty2yd3WTLPcRvlW50fid4XqFv/gBq8iQ8ksQ0Nrg=; b=aNgfWCcjrb4UEW+Wxh/0LxxEt5/6EAbu7bnWfDh36Dga4y+xm4ubPPuc tyGHK1fJYbrrlKKxTHlm1cNtu5A+3hxGGjMKkOBhO8f49q5XRhRlw9n6c /x4ot7g24Q9v+n6HvThTz6NMBIY1+32qJDzdA9CsfqqxT9cKJF9PGedTI M=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-01.qualcomm.com with ESMTP; 13 Apr 2022 08:21:47 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg02-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2022 08:21:46 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 13 Apr 2022 08:21:46 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 13 Apr 2022 08:21:42 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v7 1/4] arm64: dts: qcom: sc7280: Add nodes for soundwire and va tx rx digital macro codecs Date: Wed, 13 Apr 2022 20:51:14 +0530 Message-ID: <1649863277-31615-2-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649863277-31615-1-git-send-email-quic_srivasam@quicinc.com> References: <1649863277-31615-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SC7280 has VA, TX and RX macros with SoundWire Controllers to attach with external codecs using soundwire masters. Add these nodes for sc7280 based platforms audio use case. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 122 +++++++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 50fea0e..c0f127f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1980,6 +1980,128 @@ #clock-cells = <1>; }; + lpass_rx_macro: codec@3200000 { + compatible = "qcom,sc7280-lpass-rx-macro"; + reg = <0 0x03200000 0 0x1000>; + + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&lpass_rx_swr>; + + clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, + <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, + <&lpass_va_macro>; + clock-names = "mclk", "npl", "fsgen"; + + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, + <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; + power-domain-names ="macro", "dcodec"; + + #clock-cells = <0>; + #sound-dai-cells = <1>; + }; + + swr0: soundwire@3210000 { + compatible = "qcom,soundwire-v1.6.0"; + reg = <0 0x03210000 0 0x2000>; + + interrupts = ; + clocks = <&lpass_rx_macro>; + clock-names = "iface"; + + qcom,din-ports = <0>; + qcom,dout-ports = <5>; + + resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; + reset-names = "swr_audio_cgcr"; + + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; + qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; + qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; + + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + }; + + lpass_tx_macro: codec@3220000 { + compatible = "qcom,sc7280-lpass-tx-macro"; + reg = <0 0x03220000 0 0x1000>; + + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&lpass_tx_swr>; + + clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, + <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, + <&lpass_va_macro>; + clock-names = "mclk", "npl", "fsgen"; + + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, + <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; + power-domain-names ="macro", "dcodec"; + + #clock-cells = <0>; + #sound-dai-cells = <1>; + }; + + swr1: soundwire@3230000 { + compatible = "qcom,soundwire-v1.6.0"; + reg = <0 0x03230000 0 0x2000>; + + interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "swr_master_irq", "swr_wake_irq"; + clocks = <&lpass_tx_macro>; + clock-names = "iface"; + + qcom,din-ports = <3>; + qcom,dout-ports = <0>; + + resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; + reset-names = "swr_audio_cgcr"; + + qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; + qcom,port-offset = <1>; + + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + }; + + lpass_va_macro: codec@3370000 { + compatible = "qcom,sc7280-lpass-va-macro"; + reg = <0 0x03370000 0 0x1000>; + + status = "disabled"; + pinctrl-0 = <&lpass_dmic01>; + pinctrl-names = "default"; + + clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; + clock-names = "mclk"; + + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, + <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; + power-domain-names ="macro", "dcodec"; + + #clock-cells = <0>; + #sound-dai-cells = <1>; + }; + lpass_ag_noc: interconnect@3c40000 { reg = <0 0x03c40000 0 0xf080>; compatible = "qcom,sc7280-lpass-ag-noc";