From patchwork Thu Sep 8 08:44:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 12969802 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 719C1ECAAD5 for ; Thu, 8 Sep 2022 08:48:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231835AbiIHIst (ORCPT ); Thu, 8 Sep 2022 04:48:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57144 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231699AbiIHIsR (ORCPT ); Thu, 8 Sep 2022 04:48:17 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06C09C167C; Thu, 8 Sep 2022 01:47:31 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28887Nuh027251; Thu, 8 Sep 2022 08:45:42 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=a6N7sWpWMh2F2MPPeVjSPy6fHGAn584zh2RdDgMu+rY=; b=RrLfrWipug6M8twXsnW1Xcm/ZMw4/pjihQQ6Vkk5HTz/96idHEAXh4NmkxI5gj15x5W0 qFH8PrnccCEgon07KHjPy1/0C2YhfaFSP8PooMBDZCrxm8p9ALAFqkuNklA9ZHKxuOW8 /0WBlX+oJVzxLQ67uytx40K6MNIrhwljz+2eTX2rLUauDFM43IZonaWdbS4pp/a2rGmB DRLZdh62JCJNM65Iqw0NFj70gaZpWGWkvUOtyD1DvRGndlIh3CJry8KlheeTxhHvgwe0 e0PLjW9JIxOE73a2ekMuymiJ00WthVfDz1Qdv1YjdwaOSNPe4//2L280qqpT8yWgHO6s dw== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3jfaa5gcu4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 08 Sep 2022 08:45:42 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2888jZJS011278 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 8 Sep 2022 08:45:35 GMT Received: from taozha-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 8 Sep 2022 01:45:31 -0700 From: Tao Zhang To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach CC: Tao Zhang , Jinlong Mao , Leo Yan , Greg Kroah-Hartman , , , , Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Hao Zhang , , Subject: [PATCH 2/9] coresight-tpda: Add DSB dataset support Date: Thu, 8 Sep 2022 16:44:58 +0800 Message-ID: <1662626705-13097-3-git-send-email-quic_taozha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1662626705-13097-1-git-send-email-quic_taozha@quicinc.com> References: <1662626705-13097-1-git-send-email-quic_taozha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: sz3kV0ndf1chryM5GbxBa_wTt7fOuX_J X-Proofpoint-ORIG-GUID: sz3kV0ndf1chryM5GbxBa_wTt7fOuX_J X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-08_06,2022-09-07_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 mlxlogscore=999 lowpriorityscore=0 phishscore=0 adultscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 spamscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2209080031 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Read the DSB element size from the device tree. Set the register bit that controls the DSB element size of the corresponding port. Signed-off-by: Tao Zhang --- drivers/hwtracing/coresight/coresight-tpda.c | 62 ++++++++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpda.h | 4 ++ 2 files changed, 66 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index c8bbc75..76636a1 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -37,6 +37,15 @@ static void tpda_enable_port(struct tpda_drvdata *drvdata, int port) u32 val; val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port)); + /* + * Configure aggregator port n DSB data set element size + * Set the bit to 0 if the size is 32 + * Set the bit to 1 if the size is 64 + */ + if (drvdata->dsb_esize[port] == 32) + val &= ~TPDA_Pn_CR_DSBSIZE; + else if (drvdata->dsb_esize[port] == 64) + val |= TPDA_Pn_CR_DSBSIZE; /* Enable the port */ val |= TPDA_Pn_CR_ENA; writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port)); @@ -105,6 +114,55 @@ static const struct coresight_ops tpda_cs_ops = { .link_ops = &tpda_link_ops, }; +static int tpda_parse_dsb(struct tpda_drvdata *drvdata) +{ + int len, port, i; + const __be32 *prop; + struct device_node *node = drvdata->dev->of_node; + + /* Read the size of DSB element */ + prop = of_get_property(node, "qcom,dsb-elem-size", &len); + if (prop) { + len /= sizeof(__be32); + /* + * The read set of data is port and size, so the number of data + * is a multiple of two. And the number of data will not exceed + * two times that of the TPDA inpurts number. + */ + if (len < 2 || len >= (2 * TPDA_MAX_INPORTS) || len % 2 != 0) { + dev_err(drvdata->dev, + "Dataset DSB width entries are wrong\n"); + return -EINVAL; + } + + for (i = 0; i < len; i++) { + port = be32_to_cpu(prop[i++]); + if (port >= TPDA_MAX_INPORTS) { + dev_err(drvdata->dev, + "Wrong port specified for DSB\n"); + return -EINVAL; + } + /* Set DSB element size for corresponding port to dsb_esize*/ + drvdata->dsb_esize[port] = be32_to_cpu(prop[i]); + } + } + + return 0; +} + +static int tpda_parse_of_data(struct tpda_drvdata *drvdata) +{ + int ret; + + ret = tpda_parse_dsb(drvdata); + if (ret) { + dev_err(drvdata->dev, "Fail to get DSB data set element size\n"); + return -EINVAL; + } + + return 0; +} + static int tpda_init_default_data(struct tpda_drvdata *drvdata) { int atid; @@ -148,6 +206,10 @@ static int tpda_probe(struct amba_device *adev, const struct amba_id *id) spin_lock_init(&drvdata->spinlock); + ret = tpda_parse_of_data(drvdata); + if (ret) + return ret; + ret = tpda_init_default_data(drvdata); if (ret) return ret; diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h index 4beb332..ecc7869 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.h +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -10,6 +10,8 @@ #define TPDA_Pn_CR(n) (0x004 + (n * 4)) /* Aggregator port enable bit */ #define TPDA_Pn_CR_ENA BIT(0) +/* Aggregator port DSB data set element size bit */ +#define TPDA_Pn_CR_DSBSIZE BIT(8) #define TPDA_MAX_INPORTS 32 @@ -23,6 +25,7 @@ * @csdev: component vitals needed by the framework. * @spinlock: lock for the drvdata value. * @enable: enable status of the component. + * @dsb_esize DSB element size */ struct tpda_drvdata { void __iomem *base; @@ -30,6 +33,7 @@ struct tpda_drvdata { struct coresight_device *csdev; spinlock_t spinlock; u8 atid; + u32 dsb_esize[TPDA_MAX_INPORTS]; }; #endif /* _CORESIGHT_CORESIGHT_TPDA_H */