| Message ID | 1679036039-27157-5-git-send-email-quic_rohiagar@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add PCIe EP support for SDX65 | expand |
On 17.03.2023 07:53, Rohit Agarwal wrote: > Enable PCIe PHY on SDX65 MTP for PCIe EP. While at it, > updating status as last property for each node. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm/boot/dts/qcom-sdx65-mtp.dts | 16 +++++++++++++--- > 1 file changed, 13 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts > index ed98c83..70720e6 100644 > --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts > +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts > @@ -245,6 +245,13 @@ > status = "okay"; > }; > > +&pcie_phy { > + vdda-phy-supply = <&vreg_l1b_1p2>; > + vdda-pll-supply = <&vreg_l4b_0p88>; > + > + status = "okay"; > +}; > + > &qpic_bam { > status = "okay"; > }; > @@ -265,8 +272,9 @@ > }; > > &remoteproc_mpss { > - status = "okay"; > memory-region = <&mpss_adsp_mem>; > + > + status = "okay"; > }; > > &usb { > @@ -278,14 +286,16 @@ > }; > > &usb_hsphy { > - status = "okay"; > vdda-pll-supply = <&vreg_l4b_0p88>; > vdda33-supply = <&vreg_l10b_3p08>; > vdda18-supply = <&vreg_l5b_1p8>; > + > + status = "okay"; > }; > > &usb_qmpphy { > - status = "okay"; > vdda-phy-supply = <&vreg_l4b_0p88>; > vdda-pll-supply = <&vreg_l1b_1p2>; > + > + status = "okay"; > };
diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index ed98c83..70720e6 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -245,6 +245,13 @@ status = "okay"; }; +&pcie_phy { + vdda-phy-supply = <&vreg_l1b_1p2>; + vdda-pll-supply = <&vreg_l4b_0p88>; + + status = "okay"; +}; + &qpic_bam { status = "okay"; }; @@ -265,8 +272,9 @@ }; &remoteproc_mpss { - status = "okay"; memory-region = <&mpss_adsp_mem>; + + status = "okay"; }; &usb { @@ -278,14 +286,16 @@ }; &usb_hsphy { - status = "okay"; vdda-pll-supply = <&vreg_l4b_0p88>; vdda33-supply = <&vreg_l10b_3p08>; vdda18-supply = <&vreg_l5b_1p8>; + + status = "okay"; }; &usb_qmpphy { - status = "okay"; vdda-phy-supply = <&vreg_l4b_0p88>; vdda-pll-supply = <&vreg_l1b_1p2>; + + status = "okay"; };
Enable PCIe PHY on SDX65 MTP for PCIe EP. While at it, updating status as last property for each node. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-)